Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
Stefan Roese | 9b1e231 | 2014-10-22 12:13:19 +0200 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (C) 2014 Stefan Roese <sr@denx.de> |
Stefan Roese | 9b1e231 | 2014-10-22 12:13:19 +0200 | [diff] [blame] | 4 | */ |
| 5 | |
| 6 | #ifndef _CONFIG_DB_MV7846MP_GP_H |
| 7 | #define _CONFIG_DB_MV7846MP_GP_H |
| 8 | |
| 9 | /* |
| 10 | * High Level Configuration Options (easy to change) |
| 11 | */ |
Stefan Roese | 9b1e231 | 2014-10-22 12:13:19 +0200 | [diff] [blame] | 12 | |
Stefan Roese | 3dbf35c | 2015-08-06 14:27:36 +0200 | [diff] [blame] | 13 | /* |
| 14 | * TEXT_BASE needs to be below 16MiB, since this area is scrubbed |
| 15 | * for DDR ECC byte filling in the SPL before loading the main |
| 16 | * U-Boot into it. |
| 17 | */ |
Stefan Roese | 9b1e231 | 2014-10-22 12:13:19 +0200 | [diff] [blame] | 18 | #define CONFIG_SYS_TCLK 250000000 /* 250MHz */ |
| 19 | |
| 20 | /* |
| 21 | * Commands configuration |
| 22 | */ |
Stefan Roese | 9b1e231 | 2014-10-22 12:13:19 +0200 | [diff] [blame] | 23 | |
| 24 | /* I2C */ |
| 25 | #define CONFIG_SYS_I2C |
| 26 | #define CONFIG_SYS_I2C_MVTWSI |
Paul Kocialkowski | 2fae3e7 | 2015-04-10 23:09:51 +0200 | [diff] [blame] | 27 | #define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE |
Stefan Roese | 9b1e231 | 2014-10-22 12:13:19 +0200 | [diff] [blame] | 28 | #define CONFIG_SYS_I2C_SLAVE 0x0 |
| 29 | #define CONFIG_SYS_I2C_SPEED 100000 |
| 30 | |
| 31 | /* SPI NOR flash default params, used by sf commands */ |
Stefan Roese | 9b1e231 | 2014-10-22 12:13:19 +0200 | [diff] [blame] | 32 | |
| 33 | /* Environment in SPI NOR flash */ |
Stefan Roese | 9b1e231 | 2014-10-22 12:13:19 +0200 | [diff] [blame] | 34 | #define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */ |
| 35 | #define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */ |
| 36 | #define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64KiB sectors */ |
| 37 | |
Stefan Roese | 9b1e231 | 2014-10-22 12:13:19 +0200 | [diff] [blame] | 38 | #define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ |
Stefan Roese | 9b1e231 | 2014-10-22 12:13:19 +0200 | [diff] [blame] | 39 | |
Stefan Roese | 9b1e231 | 2014-10-22 12:13:19 +0200 | [diff] [blame] | 40 | /* |
| 41 | * mv-common.h should be defined after CMD configs since it used them |
| 42 | * to enable certain macros |
| 43 | */ |
| 44 | #include "mv-common.h" |
| 45 | |
Stefan Roese | 1a16a0c | 2015-01-19 11:33:47 +0100 | [diff] [blame] | 46 | /* |
| 47 | * Memory layout while starting into the bin_hdr via the |
| 48 | * BootROM: |
| 49 | * |
| 50 | * 0x4000.4000 - 0x4003.4000 headers space (192KiB) |
| 51 | * 0x4000.4030 bin_hdr start address |
| 52 | * 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB) |
| 53 | * 0x4007.fffc BootROM stack top |
| 54 | * |
| 55 | * The address space between 0x4007.fffc and 0x400f.fff is not locked in |
| 56 | * L2 cache thus cannot be used. |
| 57 | */ |
| 58 | |
| 59 | /* SPL */ |
| 60 | /* Defines for SPL */ |
Stefan Roese | 1a16a0c | 2015-01-19 11:33:47 +0100 | [diff] [blame] | 61 | #define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030) |
| 62 | |
| 63 | #define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10)) |
| 64 | #define CONFIG_SPL_BSS_MAX_SIZE (16 << 10) |
| 65 | |
Stefan Roese | 83097cf | 2015-11-25 07:37:00 +0100 | [diff] [blame] | 66 | #ifdef CONFIG_SPL_BUILD |
| 67 | #define CONFIG_SYS_MALLOC_SIMPLE |
| 68 | #endif |
Stefan Roese | 1a16a0c | 2015-01-19 11:33:47 +0100 | [diff] [blame] | 69 | |
| 70 | #define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) |
| 71 | #define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) |
| 72 | |
Stefan Roese | 1a16a0c | 2015-01-19 11:33:47 +0100 | [diff] [blame] | 73 | /* SPL related SPI defines */ |
Stefan Roese | 1a16a0c | 2015-01-19 11:33:47 +0100 | [diff] [blame] | 74 | |
| 75 | /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */ |
Stefan Roese | 1a16a0c | 2015-01-19 11:33:47 +0100 | [diff] [blame] | 76 | #define CONFIG_DDR_FIXED_SIZE (1 << 20) /* 1GiB */ |
Stefan Roese | ff7ad17 | 2015-12-10 15:02:38 +0100 | [diff] [blame] | 77 | #define CONFIG_BOARD_ECC_SUPPORT /* this board supports ECC */ |
Stefan Roese | 1a16a0c | 2015-01-19 11:33:47 +0100 | [diff] [blame] | 78 | |
Stefan Roese | 9b1e231 | 2014-10-22 12:13:19 +0200 | [diff] [blame] | 79 | #endif /* _CONFIG_DB_MV7846MP_GP_H */ |