Michal Simek | df7cfc7 | 2018-01-08 16:52:49 +0100 | [diff] [blame] | 1 | CONFIG_ARM=y |
| 2 | CONFIG_ARCH_ZYNQ=y |
| 3 | CONFIG_SYS_TEXT_BASE=0x4000000 |
| 4 | CONFIG_IDENT_STRING=" Xilinx Zynq ZC770 XM011 x16" |
| 5 | CONFIG_SPL_STACK_R_ADDR=0x200000 |
| 6 | # CONFIG_SPL_FAT_SUPPORT is not set |
| 7 | CONFIG_DEFAULT_DEVICE_TREE="zynq-zc770-xm011-x16" |
| 8 | CONFIG_DEBUG_UART=y |
Tom Rini | 732aa4a | 2018-02-10 16:54:38 -0500 | [diff] [blame] | 9 | CONFIG_DISTRO_DEFAULTS=y |
Michal Simek | df7cfc7 | 2018-01-08 16:52:49 +0100 | [diff] [blame] | 10 | CONFIG_FIT=y |
| 11 | CONFIG_FIT_SIGNATURE=y |
| 12 | CONFIG_FIT_VERBOSE=y |
Tom Rini | 732aa4a | 2018-02-10 16:54:38 -0500 | [diff] [blame] | 13 | # CONFIG_USE_BOOTCOMMAND is not set |
Michal Simek | df7cfc7 | 2018-01-08 16:52:49 +0100 | [diff] [blame] | 14 | # CONFIG_DISPLAY_CPUINFO is not set |
| 15 | CONFIG_SPL=y |
| 16 | CONFIG_SPL_STACK_R=y |
| 17 | CONFIG_SPL_OS_BOOT=y |
Michal Simek | df7cfc7 | 2018-01-08 16:52:49 +0100 | [diff] [blame] | 18 | CONFIG_SYS_PROMPT="Zynq> " |
Michal Simek | df7cfc7 | 2018-01-08 16:52:49 +0100 | [diff] [blame] | 19 | # CONFIG_CMD_FLASH is not set |
| 20 | CONFIG_CMD_FPGA_LOADBP=y |
| 21 | CONFIG_CMD_FPGA_LOADFS=y |
| 22 | CONFIG_CMD_FPGA_LOADMK=y |
| 23 | CONFIG_CMD_FPGA_LOADP=y |
| 24 | CONFIG_CMD_GPIO=y |
| 25 | CONFIG_CMD_NAND_LOCK_UNLOCK=y |
| 26 | # CONFIG_CMD_SETEXPR is not set |
| 27 | # CONFIG_CMD_NET is not set |
| 28 | # CONFIG_CMD_NFS is not set |
| 29 | CONFIG_CMD_CACHE=y |
Tom Rini | 732aa4a | 2018-02-10 16:54:38 -0500 | [diff] [blame] | 30 | # CONFIG_SPL_DOS_PARTITION is not set |
| 31 | # CONFIG_SPL_ISO_PARTITION is not set |
| 32 | # CONFIG_SPL_EFI_PARTITION is not set |
Michal Simek | df7cfc7 | 2018-01-08 16:52:49 +0100 | [diff] [blame] | 33 | CONFIG_OF_EMBED=y |
| 34 | CONFIG_SPL_DM_SEQ_ALIAS=y |
| 35 | CONFIG_FPGA_XILINX=y |
| 36 | CONFIG_DM_GPIO=y |
| 37 | # CONFIG_MMC is not set |
| 38 | CONFIG_DM_MMC=y |
| 39 | CONFIG_NAND=y |
| 40 | CONFIG_NAND_ZYNQ=y |
| 41 | CONFIG_DEBUG_UART_ZYNQ=y |
| 42 | CONFIG_DEBUG_UART_BASE=0xe0001000 |
| 43 | CONFIG_DEBUG_UART_CLOCK=50000000 |
| 44 | CONFIG_DEBUG_UART_ANNOUNCE=y |
| 45 | CONFIG_ZYNQ_SERIAL=y |
| 46 | CONFIG_REGEX=y |