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Peter Griffin31f327e2015-07-30 18:55:23 +01001/*
2 * (C) Copyright 2015 Linaro
3 * Peter Griffin <peter.griffin@linaro.org>
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7#include <common.h>
8#include <dm.h>
Peter Griffin0382c642015-09-10 21:55:17 +01009#include <dm/platform_data/serial_pl01x.h>
Peter Griffin31f327e2015-07-30 18:55:23 +010010#include <errno.h>
11#include <malloc.h>
12#include <netdev.h>
13#include <asm/io.h>
14#include <usb.h>
15#include <power/hi6553_pmic.h>
16#include <asm-generic/gpio.h>
17#include <asm/arch/dwmmc.h>
18#include <asm/arch/gpio.h>
19#include <asm/arch/periph.h>
20#include <asm/arch/pinmux.h>
21#include <asm/arch/hi6220.h>
Alexander Graf580be6e2016-03-04 01:09:53 +010022#include <asm/armv8/mmu.h>
Peter Griffin31f327e2015-07-30 18:55:23 +010023
24/*TODO drop this table in favour of device tree */
25static const struct hikey_gpio_platdata hi6220_gpio[] = {
26 { 0, HI6220_GPIO_BASE(0)},
27 { 1, HI6220_GPIO_BASE(1)},
28 { 2, HI6220_GPIO_BASE(2)},
29 { 3, HI6220_GPIO_BASE(3)},
30 { 4, HI6220_GPIO_BASE(4)},
31 { 5, HI6220_GPIO_BASE(5)},
32 { 6, HI6220_GPIO_BASE(6)},
33 { 7, HI6220_GPIO_BASE(7)},
34 { 8, HI6220_GPIO_BASE(8)},
35 { 9, HI6220_GPIO_BASE(9)},
36 { 10, HI6220_GPIO_BASE(10)},
37 { 11, HI6220_GPIO_BASE(11)},
38 { 12, HI6220_GPIO_BASE(12)},
39 { 13, HI6220_GPIO_BASE(13)},
40 { 14, HI6220_GPIO_BASE(14)},
41 { 15, HI6220_GPIO_BASE(15)},
42 { 16, HI6220_GPIO_BASE(16)},
43 { 17, HI6220_GPIO_BASE(17)},
44 { 18, HI6220_GPIO_BASE(18)},
45 { 19, HI6220_GPIO_BASE(19)},
46
47};
48
49U_BOOT_DEVICES(hi6220_gpios) = {
50 { "gpio_hi6220", &hi6220_gpio[0] },
51 { "gpio_hi6220", &hi6220_gpio[1] },
52 { "gpio_hi6220", &hi6220_gpio[2] },
53 { "gpio_hi6220", &hi6220_gpio[3] },
54 { "gpio_hi6220", &hi6220_gpio[4] },
55 { "gpio_hi6220", &hi6220_gpio[5] },
56 { "gpio_hi6220", &hi6220_gpio[6] },
57 { "gpio_hi6220", &hi6220_gpio[7] },
58 { "gpio_hi6220", &hi6220_gpio[8] },
59 { "gpio_hi6220", &hi6220_gpio[9] },
60 { "gpio_hi6220", &hi6220_gpio[10] },
61 { "gpio_hi6220", &hi6220_gpio[11] },
62 { "gpio_hi6220", &hi6220_gpio[12] },
63 { "gpio_hi6220", &hi6220_gpio[13] },
64 { "gpio_hi6220", &hi6220_gpio[14] },
65 { "gpio_hi6220", &hi6220_gpio[15] },
66 { "gpio_hi6220", &hi6220_gpio[16] },
67 { "gpio_hi6220", &hi6220_gpio[17] },
68 { "gpio_hi6220", &hi6220_gpio[18] },
69 { "gpio_hi6220", &hi6220_gpio[19] },
70};
71
72DECLARE_GLOBAL_DATA_PTR;
73
Peter Griffinc97c37a2016-04-20 17:13:59 +010074#if !CONFIG_IS_ENABLED(OF_CONTROL)
75
Peter Griffin0382c642015-09-10 21:55:17 +010076static const struct pl01x_serial_platdata serial_platdata = {
77#if CONFIG_CONS_INDEX == 1
78 .base = HI6220_UART0_BASE,
79#elif CONFIG_CONS_INDEX == 4
80 .base = HI6220_UART3_BASE,
81#else
Vagrant Cascadiane1643ed2016-03-15 12:11:13 -070082#error "Unsupported console index value."
Peter Griffin0382c642015-09-10 21:55:17 +010083#endif
84 .type = TYPE_PL011,
85 .clock = 19200000
86};
87
88U_BOOT_DEVICE(hikey_seriala) = {
89 .name = "serial_pl01x",
90 .platdata = &serial_platdata,
91};
Peter Griffinc97c37a2016-04-20 17:13:59 +010092#endif
Peter Griffin0382c642015-09-10 21:55:17 +010093
Alexander Graf580be6e2016-03-04 01:09:53 +010094static struct mm_region hikey_mem_map[] = {
95 {
96 .base = 0x0UL,
97 .size = 0x80000000UL,
98 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
99 PTE_BLOCK_INNER_SHARE
100 }, {
101 .base = 0x80000000UL,
102 .size = 0x80000000UL,
103 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
104 PTE_BLOCK_NON_SHARE |
105 PTE_BLOCK_PXN | PTE_BLOCK_UXN
106 }, {
107 /* List terminator */
108 0,
109 }
110};
111
112struct mm_region *mem_map = hikey_mem_map;
113
Peter Griffin0382c642015-09-10 21:55:17 +0100114#ifdef CONFIG_BOARD_EARLY_INIT_F
115int board_uart_init(void)
116{
117 switch (CONFIG_CONS_INDEX) {
118 case 1:
119 hi6220_pinmux_config(PERIPH_ID_UART0);
120 break;
121 case 4:
122 hi6220_pinmux_config(PERIPH_ID_UART3);
123 break;
124 default:
125 debug("%s: Unsupported UART selected\n", __func__);
126 return -1;
127 }
128
129 return 0;
130}
131
132int board_early_init_f(void)
133{
134 board_uart_init();
135 return 0;
136}
137#endif
138
Peter Griffin31f327e2015-07-30 18:55:23 +0100139struct peri_sc_periph_regs *peri_sc =
140 (struct peri_sc_periph_regs *)HI6220_PERI_BASE;
141
142struct alwayson_sc_regs *ao_sc =
143 (struct alwayson_sc_regs *)ALWAYSON_CTRL_BASE;
144
145/* status offset from enable reg */
146#define STAT_EN_OFF 0x2
147
148void hi6220_clk_enable(u32 bitfield, unsigned int *clk_base)
149{
150 uint32_t data;
151
152 data = readl(clk_base);
153 data |= bitfield;
154
155 writel(bitfield, clk_base);
156 do {
157 data = readl(clk_base + STAT_EN_OFF);
158 } while ((data & bitfield) == 0);
159}
160
161/* status offset from disable reg */
162#define STAT_DIS_OFF 0x1
163
164void hi6220_clk_disable(u32 bitfield, unsigned int *clk_base)
165{
166 uint32_t data;
167
168 data = readl(clk_base);
169 data |= bitfield;
170
171 writel(data, clk_base);
172 do {
173 data = readl(clk_base + STAT_DIS_OFF);
174 } while (data & bitfield);
175}
176
177#define EYE_PATTERN 0x70533483
178
179int board_usb_init(int index, enum usb_init_type init)
180{
181 unsigned int data;
182
183 /* enable USB clock */
184 hi6220_clk_enable(PERI_CLK0_USBOTG, &peri_sc->clk0_en);
185
186 /* take usb IPs out of reset */
187 writel(PERI_RST0_USBOTG_BUS | PERI_RST0_POR_PICOPHY |
188 PERI_RST0_USBOTG | PERI_RST0_USBOTG_32K,
189 &peri_sc->rst0_dis);
190 do {
191 data = readl(&peri_sc->rst0_stat);
192 data &= PERI_RST0_USBOTG_BUS | PERI_RST0_POR_PICOPHY |
193 PERI_RST0_USBOTG | PERI_RST0_USBOTG_32K;
194 } while (data);
195
196 /*CTRL 5*/
197 data = readl(&peri_sc->ctrl5);
198 data &= ~PERI_CTRL5_PICOPHY_BC_MODE;
199 data |= PERI_CTRL5_USBOTG_RES_SEL | PERI_CTRL5_PICOPHY_ACAENB;
200 data |= 0x300;
201 writel(data, &peri_sc->ctrl5);
202
203 /*CTRL 4*/
204
205 /* configure USB PHY */
206 data = readl(&peri_sc->ctrl4);
207
208 /* make PHY out of low power mode */
209 data &= ~PERI_CTRL4_PICO_SIDDQ;
210 data &= ~PERI_CTRL4_PICO_OGDISABLE;
211 data |= PERI_CTRL4_PICO_VBUSVLDEXTSEL | PERI_CTRL4_PICO_VBUSVLDEXT;
212 writel(data, &peri_sc->ctrl4);
213
214 writel(EYE_PATTERN, &peri_sc->ctrl8);
215
216 mdelay(5);
217 return 0;
218}
219
220static int config_sd_carddetect(void)
221{
222 int ret;
223
224 /* configure GPIO8 as nopull */
225 writel(0, 0xf8001830);
226
227 gpio_request(8, "SD CD");
228
229 gpio_direction_input(8);
230 ret = gpio_get_value(8);
231
232 if (!ret) {
233 printf("%s: SD card present\n", __func__);
234 return 1;
235 }
236
237 printf("%s: SD card not present\n", __func__);
238 return 0;
239}
240
241
242static void mmc1_init_pll(void)
243{
244 uint32_t data;
245
246 /* select SYSPLL as the source of MMC1 */
247 /* select SYSPLL as the source of MUX1 (SC_CLK_SEL0) */
248 writel(1 << 11 | 1 << 27, &peri_sc->clk0_sel);
249 do {
250 data = readl(&peri_sc->clk0_sel);
251 } while (!(data & (1 << 11)));
252
253 /* select MUX1 as the source of MUX2 (SC_CLK_SEL0) */
254 writel(1 << 30, &peri_sc->clk0_sel);
255 do {
256 data = readl(&peri_sc->clk0_sel);
257 } while (data & (1 << 14));
258
259 hi6220_clk_enable(PERI_CLK0_MMC1, &peri_sc->clk0_en);
260
261 hi6220_clk_enable(PERI_CLK12_MMC1_SRC, &peri_sc->clk12_en);
262
263 do {
264 /* 1.2GHz / 50 = 24MHz */
265 writel(0x31 | (1 << 7), &peri_sc->clkcfg8bit2);
266 data = readl(&peri_sc->clkcfg8bit2);
267 } while ((data & 0x31) != 0x31);
268}
269
270static void mmc1_reset_clk(void)
271{
272 unsigned int data;
273
274 /* disable mmc1 bus clock */
275 hi6220_clk_disable(PERI_CLK0_MMC1, &peri_sc->clk0_dis);
276
277 /* enable mmc1 bus clock */
278 hi6220_clk_enable(PERI_CLK0_MMC1, &peri_sc->clk0_en);
279
280 /* reset mmc1 clock domain */
281 writel(PERI_RST0_MMC1, &peri_sc->rst0_en);
282
283 /* bypass mmc1 clock phase */
284 data = readl(&peri_sc->ctrl2);
285 data |= 3 << 2;
286 writel(data, &peri_sc->ctrl2);
287
288 /* disable low power */
289 data = readl(&peri_sc->ctrl13);
290 data |= 1 << 4;
291 writel(data, &peri_sc->ctrl13);
292 do {
293 data = readl(&peri_sc->rst0_stat);
294 } while (!(data & PERI_RST0_MMC1));
295
296 /* unreset mmc0 clock domain */
297 writel(PERI_RST0_MMC1, &peri_sc->rst0_dis);
298 do {
299 data = readl(&peri_sc->rst0_stat);
300 } while (data & PERI_RST0_MMC1);
301}
302
303/* PMU SSI is the IP that maps the external PMU hi6553 registers as IO */
304static void hi6220_pmussi_init(void)
305{
306 uint32_t data;
307
308 /* Take PMUSSI out of reset */
309 writel(ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_PMUSSI_N,
310 &ao_sc->rst4_dis);
311 do {
312 data = readl(&ao_sc->rst4_stat);
313 } while (data & ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_PMUSSI_N);
314
315 /* set PMU SSI clock latency for read operation */
316 data = readl(&ao_sc->mcu_subsys_ctrl3);
317 data &= ~ALWAYSON_SC_MCU_SUBSYS_CTRL3_RCLK_MASK;
318 data |= ALWAYSON_SC_MCU_SUBSYS_CTRL3_RCLK_3;
319 writel(data, &ao_sc->mcu_subsys_ctrl3);
320
321 /* enable PMUSSI clock */
322 data = ALWAYSON_SC_PERIPH_CLK5_EN_PCLK_PMUSSI_CCPU |
323 ALWAYSON_SC_PERIPH_CLK5_EN_PCLK_PMUSSI_MCU;
324
325 hi6220_clk_enable(data, &ao_sc->clk5_en);
326
327 /* Output high to PMIC on PWR_HOLD_GPIO0_0 */
328 gpio_request(0, "PWR_HOLD_GPIO0_0");
329 gpio_direction_output(0, 1);
330}
331
332int misc_init_r(void)
333{
334 return 0;
335}
336
337int board_init(void)
338{
Peter Griffin31f327e2015-07-30 18:55:23 +0100339 return 0;
340}
341
342#ifdef CONFIG_GENERIC_MMC
343
344static int init_dwmmc(void)
345{
346 int ret;
347
348#ifdef CONFIG_DWMMC
349
350 /* mmc0 clocks are already configured by ATF */
351 ret = hi6220_pinmux_config(PERIPH_ID_SDMMC0);
352 if (ret)
353 printf("%s: Error configuring pinmux for eMMC (%d)\n"
354 , __func__, ret);
355
356 ret |= hi6220_dwmci_add_port(0, HI6220_MMC0_BASE, 8);
357 if (ret)
358 printf("%s: Error adding eMMC port (%d)\n", __func__, ret);
359
360
361 /* take mmc1 (sd slot) out of reset, configure clocks and pinmuxing */
362 mmc1_init_pll();
363 mmc1_reset_clk();
364
365 ret |= hi6220_pinmux_config(PERIPH_ID_SDMMC1);
366 if (ret)
367 printf("%s: Error configuring pinmux for eMMC (%d)\n"
368 , __func__, ret);
369
370 config_sd_carddetect();
371
372 ret |= hi6220_dwmci_add_port(1, HI6220_MMC1_BASE, 4);
373 if (ret)
374 printf("%s: Error adding SD port (%d)\n", __func__, ret);
375
376#endif
377 return ret;
378}
379
380/* setup board specific PMIC */
381int power_init_board(void)
382{
383 /* init the hi6220 pmussi ip */
384 hi6220_pmussi_init();
385
386 power_hi6553_init((u8 *)HI6220_PMUSSI_BASE);
387
388 return 0;
389}
390
391int board_mmc_init(bd_t *bis)
392{
393 int ret;
394
395 /* add the eMMC and sd ports */
396 ret = init_dwmmc();
397
398 if (ret)
399 debug("init_dwmmc failed\n");
400
401 return ret;
402}
403#endif
404
405int dram_init(void)
406{
407 gd->ram_size = PHYS_SDRAM_1_SIZE;
408 return 0;
409}
410
411void dram_init_banksize(void)
412{
413 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
414 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
415}
416
417/* Use the Watchdog to cause reset */
418void reset_cpu(ulong addr)
419{
420 /* TODO program the watchdog */
421}