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git01.mediatek.com / filogic / uboot / c960c0a847cfb44ec64399fdfcaba35e76400db2 / . / board / freescale / mx6memcal / Kconfig
blob: 9987cba5dcb7aa3962200d55cc148d18b8f40734 [file] [log] [blame]
Eric Nelson4c644792017-12-11 13:52:11 -0200[diff] [blame]1if TARGET_MX6MEMCAL
2
3config SYS_BOARD
4 default "mx6memcal"
5
6config SYS_VENDOR
7 default "freescale"
8
9config SYS_CONFIG_NAME
10 default "mx6memcal"
11
12menu "mx6memcal specifics"
13choice
14 prompt "Serial console"
15 help
16 Either UART1 or UART2 will be used as the console for
17 displaying the calibration values or errors.
18
19config SERIAL_CONSOLE_UART1
20 bool "UART1"
21 help
22 Select this if your board uses UART1 for its' console.
23
24config SERIAL_CONSOLE_UART2
25 bool "UART2"
26 help
27 Select this if your board uses UART2 for its' console.
28
29endchoice
30
31choice
32 prompt "UART pads"
33 help
34 Select the RX and TX pads used for your serial console.
35 The choices below reflect the most commonly used options
36 for your UART.
37
38 config UART2_EIM_D26_27
39 bool "UART2 on EIM_D26/27 (SabreLite, Nitrogen6x)"
40 depends on SERIAL_CONSOLE_UART2
41 help
42 Choose this configuration if you're using pads
43 EIM_D26 and D27 for a console on UART2.
44 This is typical for designs that are based on the
45 NXP SABRELite.
46
47 config UART1_CSI0_DAT10_11
Fabio Estevam1cea47a2018-01-03 12:55:34 -0200[diff] [blame]48 bool "UART1 on CSI0_DAT10/11 (Wand, SabreSD)"
Eric Nelson4c644792017-12-11 13:52:11 -0200[diff] [blame]49 depends on SERIAL_CONSOLE_UART1
50 help
51 Choose this configuration if you're using pads
52 CSI0_DAT10 and DAT11 for a console on UART1 as
Fabio Estevam1cea47a2018-01-03 12:55:34 -0200[diff] [blame]53 is done on the i.MX6 Wand board and i.MX6 SabreSD.
Eric Nelson4c644792017-12-11 13:52:11 -0200[diff] [blame]54
55 config UART1_UART1
56 bool "UART1 on UART1 (i.MX6SL EVK, WaRP)"
57 depends on SERIAL_CONSOLE_UART1
58 help
59 Choose this configuration if you're using pads
60 UART1_TXD/RXD for a console on UART1 as is done
61 on most i.MX6SL designs.
62
63endchoice
64
65config IMXIMAGE_OUTPUT
66 bool "Include output for imximage .cfg files"
67 default y
68 help
69 Say "Y" if you want output formatted for use in non-SPL
70 (DCD-style) configuration files.
71
72config DDRWIDTH
73 int "DDR bus width"
74 default 64
75 help
76 Select either 32 or 64 to reflect the DDR bus width.
77
78config DDRCS
79 int "DDR chip selects"
80 default 2
81 range 1 2
82 help
83 Select the number of chip selects used in your board design
84
85choice
86 prompt "Memory type"
87 help
88 Select the type of DDR (DDR3 or LPDDR2) used on your design
89
90config DDR3
91 bool "DDR3"
92 help
93 Select this if your board design uses DDR3.
94
95config LPDDR2
96 bool "LPDDR2"
97 help
98 Select this if your board design uses LPDDR2.
99
100endchoice
101
102choice
103 prompt "Memory device"
104
105config MT41K512M16TNA
106 bool "Micron MT41K512M16TNA 512Mx16 (1GiB/chip)"
107 depends on DDR3
108
109config MT41K128M16JT
110 bool "Micron MT41K128M16JT 128Mx16 (256 MiB/chip)"
111 depends on DDR3
112
113config H5TQ4G63AFR
114 bool "Hynix H5TQ4G63AFR 256Mx16 (512 MiB/chip)"
115 depends on DDR3
116
117config H5TQ2G63DFR
118 bool "Hynix H5TQ2G63DFR 128Mx16 (256 MiB/chip)"
119 depends on DDR3
120
121config MT42L256M32D2LG
122 bool "Micron MT42L256M32D2LG LPDDR2 256Mx32 (1GiB/chip)"
123 depends on LPDDR2
124
125config MT29PZZZ4D4BKESK
126 bool "Micron MT29PZZZ4D4BKESK multi-chip 512MiB LPDDR2/4GiB eMMC"
127 depends on LPDDR2
128
129endchoice
130
131config DDR_ODT
132 int "DDR On-die-termination"
133 default 2
134 range 0 7
135 help
136 Enter the on-die termination value as an index defined for
137 IOMUX settings for PAD_DRAM_SDCLK0_P and others.
138 0 == Disabled
139 1 == 120 Ohm
140 2 == 60 Ohm
141 3 == 40 Ohm
142 4 == 30 Ohm
143 5 == 24 Ohm
144 6 == 20 Ohm
145 7 == 17 Ohm
146 Value will be applied to all clock and data lines
147
148
149config DRAM_DRIVE_STRENGTH
150 int "DRAM Drive strength"
151 default 6
152 range 0 7
153 help
154 Enter drive strength as an index defined for IOMUX settings
155 for GRP_B1DS and others.
156 0 == Hi Z
157 6 == 40 Ohm (default)
158 7 == 34 Ohm
159 Value will be applied to all clock and data lines
160
161config RTT_NOM
162 int "RTT_NOM"
163 default 1
164 range 1 2
165 help
166 Enter the RTT_NOM selector
167 1 == RZQ/4 (60ohm)
168 2 == RZQ/2 (120ohm)
169
170config RTT_WR
171 int "RTT_WR"
172 default 1
173 range 0 2
174 help
175 Enter the RTT_WR selector for MR2
176 0 == Dynamic ODT disabled
177 1 == RZQ/4 (60ohm)
178 2 == RZQ/2 (120ohm)
179
180config RALAT
181 int "Read additional latency"
182 default 5
183 range 0 7
184 help
185 Enter a latency in number of cycles. This will be added to
186 CAS and internal delays for which the MMDC will retrieve the
187 read data from the internal FIFO.
188 This is used to compensate for board/chip delays.
189
190config WALAT
191 int "Write additional latency"
192 default 0
193 range 0 7
194 help
195 Enter a latency in number of cycles. This will be added to
196 CAS and internal delays for which the MMDC will retrieve the
197 read data from the internal FIFO
198 This is used to compensate for board/chip delays.
199
200config REFSEL
201 int "Refresh period"
202 range 0 3
203 default 1
204 help
205 Select the DDR refresh period.
206 See the description of bitfield REF_SEL in the reference manual
207 for details.
208 0 == disabled
209 1 == 32 kHz
210 2 == 64 kHz
211 3 == fast counter
212
213config REFR
214 int "Number of refreshes"
215 range 0 7
216 default 7
217 help
218 This selects the number of refreshes (-1) during each period.
219 i.e.:
220 0 == 1 refresh (tRFC)
221 7 == 8 refreshes (tRFC*8)
222 See the description of MDREF[REFR] in the reference manual for
223 details.
224
225endmenu
226endif
227