blob: a7f5e9116552fb873c3329456dc2a0264894dc9b [file] [log] [blame]
Heiko Stuebneraff82aa2019-07-16 22:17:13 +02001/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * (C) Copyright 2017 Rockchip Electronics Co., Ltd
4 */
5
6#ifndef __CONFIG_PX30_COMMON_H
7#define __CONFIG_PX30_COMMON_H
8
9#include "rockchip-common.h"
10
11#define CONFIG_SYS_CBSIZE 1024
Heiko Stuebneraff82aa2019-07-16 22:17:13 +020012
13#define CONFIG_SYS_NS16550_MEM32
14
Heiko Stuebneraff82aa2019-07-16 22:17:13 +020015/* FIXME: ff020000 is pmu_mem (10k), while ff0e0000 is regular int_mem */
16#define CONFIG_IRAM_BASE 0xff020000
17
18#define CONFIG_SYS_INIT_SP_ADDR 0x00400000
Heiko Stuebneraff82aa2019-07-16 22:17:13 +020019#define CONFIG_SPL_STACK 0x00400000
20#define CONFIG_SPL_MAX_SIZE 0x20000
21#define CONFIG_SPL_BSS_START_ADDR 0x4000000
22#define CONFIG_SPL_BSS_MAX_SIZE 0x4000
23#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */
24
25#define GICD_BASE 0xff131000
26#define GICC_BASE 0xff132000
27
28#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */
29
Heiko Stuebneraff82aa2019-07-16 22:17:13 +020030#define CONFIG_SYS_SDRAM_BASE 0
31#define SDRAM_MAX_SIZE 0xff000000
32#define SDRAM_BANK_SIZE (2UL << 30)
33
34#ifndef CONFIG_SPL_BUILD
35
36#define ENV_MEM_LAYOUT_SETTINGS \
37 "scriptaddr=0x00500000\0" \
38 "pxefile_addr_r=0x00600000\0" \
39 "fdt_addr_r=0x08300000\0" \
40 "kernel_addr_r=0x00280000\0" \
41 "kernel_addr_c=0x03e80000\0" \
42 "ramdisk_addr_r=0x0a200000\0"
43
44#include <config_distro_bootcmd.h>
45#define CONFIG_EXTRA_ENV_SETTINGS \
46 ENV_MEM_LAYOUT_SETTINGS \
47 "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
48 "partitions=" PARTS_DEFAULT \
49 ROCKCHIP_DEVICE_SETTINGS \
50 BOOTENV
51
52#endif
53
54#endif