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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Andrea Scian4bbf3ca2015-03-20 16:00:25 +01002/*
3 * Xilinx Zynq GPIO device driver
4 *
5 * Copyright (C) 2015 DAVE Embedded Systems <devel@dave.eu>
6 *
7 * Most of code taken from linux kernel driver (linux/drivers/gpio/gpio-zynq.c)
8 * Copyright (C) 2009 - 2014 Xilinx, Inc.
Andrea Scian4bbf3ca2015-03-20 16:00:25 +01009 */
10
11#include <common.h>
12#include <asm/gpio.h>
13#include <asm/io.h>
Masahiro Yamada56a931c2016-09-21 11:28:55 +090014#include <linux/errno.h>
Siva Durga Prasad Paladugu6fea9012016-03-10 16:27:38 +053015#include <dm.h>
16#include <fdtdec.h>
17
Siva Durga Prasad Paladugu228a1f92016-03-10 16:27:42 +053018/* Maximum banks */
19#define ZYNQ_GPIO_MAX_BANK 4
20
21#define ZYNQ_GPIO_BANK0_NGPIO 32
22#define ZYNQ_GPIO_BANK1_NGPIO 22
23#define ZYNQ_GPIO_BANK2_NGPIO 32
24#define ZYNQ_GPIO_BANK3_NGPIO 32
25
26#define ZYNQ_GPIO_NR_GPIOS (ZYNQ_GPIO_BANK0_NGPIO + \
27 ZYNQ_GPIO_BANK1_NGPIO + \
28 ZYNQ_GPIO_BANK2_NGPIO + \
29 ZYNQ_GPIO_BANK3_NGPIO)
30
Siva Durga Prasad Paladugu1904ce52016-03-10 16:27:43 +053031#define ZYNQMP_GPIO_MAX_BANK 6
32
33#define ZYNQMP_GPIO_BANK0_NGPIO 26
34#define ZYNQMP_GPIO_BANK1_NGPIO 26
35#define ZYNQMP_GPIO_BANK2_NGPIO 26
36#define ZYNQMP_GPIO_BANK3_NGPIO 32
37#define ZYNQMP_GPIO_BANK4_NGPIO 32
38#define ZYNQMP_GPIO_BANK5_NGPIO 32
39
40#define ZYNQMP_GPIO_NR_GPIOS 174
41
42#define ZYNQ_GPIO_BANK0_PIN_MIN(str) 0
43#define ZYNQ_GPIO_BANK0_PIN_MAX(str) (ZYNQ_GPIO_BANK0_PIN_MIN(str) + \
44 ZYNQ##str##_GPIO_BANK0_NGPIO - 1)
45#define ZYNQ_GPIO_BANK1_PIN_MIN(str) (ZYNQ_GPIO_BANK0_PIN_MAX(str) + 1)
46#define ZYNQ_GPIO_BANK1_PIN_MAX(str) (ZYNQ_GPIO_BANK1_PIN_MIN(str) + \
47 ZYNQ##str##_GPIO_BANK1_NGPIO - 1)
48#define ZYNQ_GPIO_BANK2_PIN_MIN(str) (ZYNQ_GPIO_BANK1_PIN_MAX(str) + 1)
49#define ZYNQ_GPIO_BANK2_PIN_MAX(str) (ZYNQ_GPIO_BANK2_PIN_MIN(str) + \
50 ZYNQ##str##_GPIO_BANK2_NGPIO - 1)
51#define ZYNQ_GPIO_BANK3_PIN_MIN(str) (ZYNQ_GPIO_BANK2_PIN_MAX(str) + 1)
52#define ZYNQ_GPIO_BANK3_PIN_MAX(str) (ZYNQ_GPIO_BANK3_PIN_MIN(str) + \
53 ZYNQ##str##_GPIO_BANK3_NGPIO - 1)
54#define ZYNQ_GPIO_BANK4_PIN_MIN(str) (ZYNQ_GPIO_BANK3_PIN_MAX(str) + 1)
55#define ZYNQ_GPIO_BANK4_PIN_MAX(str) (ZYNQ_GPIO_BANK4_PIN_MIN(str) + \
56 ZYNQ##str##_GPIO_BANK4_NGPIO - 1)
57#define ZYNQ_GPIO_BANK5_PIN_MIN(str) (ZYNQ_GPIO_BANK4_PIN_MAX(str) + 1)
58#define ZYNQ_GPIO_BANK5_PIN_MAX(str) (ZYNQ_GPIO_BANK5_PIN_MIN(str) + \
59 ZYNQ##str##_GPIO_BANK5_NGPIO - 1)
Siva Durga Prasad Paladugu228a1f92016-03-10 16:27:42 +053060
61/* Register offsets for the GPIO device */
62/* LSW Mask & Data -WO */
63#define ZYNQ_GPIO_DATA_LSW_OFFSET(BANK) (0x000 + (8 * BANK))
64/* MSW Mask & Data -WO */
65#define ZYNQ_GPIO_DATA_MSW_OFFSET(BANK) (0x004 + (8 * BANK))
66/* Data Register-RW */
67#define ZYNQ_GPIO_DATA_RO_OFFSET(BANK) (0x060 + (4 * BANK))
68/* Direction mode reg-RW */
69#define ZYNQ_GPIO_DIRM_OFFSET(BANK) (0x204 + (0x40 * BANK))
70/* Output enable reg-RW */
71#define ZYNQ_GPIO_OUTEN_OFFSET(BANK) (0x208 + (0x40 * BANK))
72/* Interrupt mask reg-RO */
73#define ZYNQ_GPIO_INTMASK_OFFSET(BANK) (0x20C + (0x40 * BANK))
74/* Interrupt enable reg-WO */
75#define ZYNQ_GPIO_INTEN_OFFSET(BANK) (0x210 + (0x40 * BANK))
76/* Interrupt disable reg-WO */
77#define ZYNQ_GPIO_INTDIS_OFFSET(BANK) (0x214 + (0x40 * BANK))
78/* Interrupt status reg-RO */
79#define ZYNQ_GPIO_INTSTS_OFFSET(BANK) (0x218 + (0x40 * BANK))
80/* Interrupt type reg-RW */
81#define ZYNQ_GPIO_INTTYPE_OFFSET(BANK) (0x21C + (0x40 * BANK))
82/* Interrupt polarity reg-RW */
83#define ZYNQ_GPIO_INTPOL_OFFSET(BANK) (0x220 + (0x40 * BANK))
84/* Interrupt on any, reg-RW */
85#define ZYNQ_GPIO_INTANY_OFFSET(BANK) (0x224 + (0x40 * BANK))
86
87/* Disable all interrupts mask */
88#define ZYNQ_GPIO_IXR_DISABLE_ALL 0xFFFFFFFF
89
90/* Mid pin number of a bank */
91#define ZYNQ_GPIO_MID_PIN_NUM 16
92
93/* GPIO upper 16 bit mask */
94#define ZYNQ_GPIO_UPPER_MASK 0xFFFF0000
95
Shubhrajyoti Datta470e5fb2019-09-18 12:10:31 +053096#define PMC_GPIO_NR_GPIOS 116
97#define PMC_GPIO_MAX_BANK 5
98
Vipul Kumarc7824172018-07-20 14:36:49 +053099struct zynq_gpio_platdata {
Siva Durga Prasad Paladugu6fea9012016-03-10 16:27:38 +0530100 phys_addr_t base;
Siva Durga Prasad Paladugu1904ce52016-03-10 16:27:43 +0530101 const struct zynq_platform_data *p_data;
102};
103
104/**
105 * struct zynq_platform_data - zynq gpio platform data structure
106 * @label: string to store in gpio->label
107 * @ngpio: max number of gpio pins
108 * @max_bank: maximum number of gpio banks
109 * @bank_min: this array represents bank's min pin
110 * @bank_max: this array represents bank's max pin
111 */
112struct zynq_platform_data {
113 const char *label;
114 u16 ngpio;
Michal Simek615900b2018-06-13 13:22:08 +0200115 u32 max_bank;
116 u32 bank_min[ZYNQMP_GPIO_MAX_BANK];
117 u32 bank_max[ZYNQMP_GPIO_MAX_BANK];
Siva Durga Prasad Paladugu1904ce52016-03-10 16:27:43 +0530118};
119
Ashok Reddy Somac8a53072019-09-16 03:35:16 -0600120#define VERSAL_GPIO_NR_GPIOS 58
121#define VERSAL_GPIO_MAX_BANK 4
122
123static const struct zynq_platform_data versal_gpio_def = {
124 .label = "versal_gpio",
125 .ngpio = VERSAL_GPIO_NR_GPIOS,
126 .max_bank = VERSAL_GPIO_MAX_BANK,
127 .bank_min[0] = 0,
128 .bank_max[0] = 25,
129 .bank_min[3] = 26,
130 .bank_max[3] = 57,
131};
132
Shubhrajyoti Datta470e5fb2019-09-18 12:10:31 +0530133static const struct zynq_platform_data pmc_gpio_def = {
134 .label = "pmc_gpio",
135 .ngpio = PMC_GPIO_NR_GPIOS,
136 .max_bank = PMC_GPIO_MAX_BANK,
137 .bank_min[0] = 0,
138 .bank_max[0] = 25,
139 .bank_min[1] = 26,
140 .bank_max[1] = 51,
141 .bank_min[3] = 52,
142 .bank_max[3] = 83,
143 .bank_min[4] = 84,
144 .bank_max[4] = 115,
145};
146
Siva Durga Prasad Paladugu1904ce52016-03-10 16:27:43 +0530147static const struct zynq_platform_data zynqmp_gpio_def = {
148 .label = "zynqmp_gpio",
149 .ngpio = ZYNQMP_GPIO_NR_GPIOS,
150 .max_bank = ZYNQMP_GPIO_MAX_BANK,
151 .bank_min[0] = ZYNQ_GPIO_BANK0_PIN_MIN(MP),
152 .bank_max[0] = ZYNQ_GPIO_BANK0_PIN_MAX(MP),
153 .bank_min[1] = ZYNQ_GPIO_BANK1_PIN_MIN(MP),
154 .bank_max[1] = ZYNQ_GPIO_BANK1_PIN_MAX(MP),
155 .bank_min[2] = ZYNQ_GPIO_BANK2_PIN_MIN(MP),
156 .bank_max[2] = ZYNQ_GPIO_BANK2_PIN_MAX(MP),
157 .bank_min[3] = ZYNQ_GPIO_BANK3_PIN_MIN(MP),
158 .bank_max[3] = ZYNQ_GPIO_BANK3_PIN_MAX(MP),
159 .bank_min[4] = ZYNQ_GPIO_BANK4_PIN_MIN(MP),
160 .bank_max[4] = ZYNQ_GPIO_BANK4_PIN_MAX(MP),
161 .bank_min[5] = ZYNQ_GPIO_BANK5_PIN_MIN(MP),
162 .bank_max[5] = ZYNQ_GPIO_BANK5_PIN_MAX(MP),
163};
164
165static const struct zynq_platform_data zynq_gpio_def = {
166 .label = "zynq_gpio",
167 .ngpio = ZYNQ_GPIO_NR_GPIOS,
168 .max_bank = ZYNQ_GPIO_MAX_BANK,
169 .bank_min[0] = ZYNQ_GPIO_BANK0_PIN_MIN(),
170 .bank_max[0] = ZYNQ_GPIO_BANK0_PIN_MAX(),
171 .bank_min[1] = ZYNQ_GPIO_BANK1_PIN_MIN(),
172 .bank_max[1] = ZYNQ_GPIO_BANK1_PIN_MAX(),
173 .bank_min[2] = ZYNQ_GPIO_BANK2_PIN_MIN(),
174 .bank_max[2] = ZYNQ_GPIO_BANK2_PIN_MAX(),
175 .bank_min[3] = ZYNQ_GPIO_BANK3_PIN_MIN(),
176 .bank_max[3] = ZYNQ_GPIO_BANK3_PIN_MAX(),
Siva Durga Prasad Paladugu6fea9012016-03-10 16:27:38 +0530177};
Siva Durga Prasad Paladugu6fea9012016-03-10 16:27:38 +0530178
Andrea Scian4bbf3ca2015-03-20 16:00:25 +0100179/**
180 * zynq_gpio_get_bank_pin - Get the bank number and pin number within that bank
181 * for a given pin in the GPIO device
182 * @pin_num: gpio pin number within the device
183 * @bank_num: an output parameter used to return the bank number of the gpio
184 * pin
185 * @bank_pin_num: an output parameter used to return pin number within a bank
186 * for the given gpio pin
187 *
188 * Returns the bank number and pin offset within the bank.
189 */
190static inline void zynq_gpio_get_bank_pin(unsigned int pin_num,
191 unsigned int *bank_num,
Siva Durga Prasad Paladugu1904ce52016-03-10 16:27:43 +0530192 unsigned int *bank_pin_num,
193 struct udevice *dev)
Andrea Scian4bbf3ca2015-03-20 16:00:25 +0100194{
Vipul Kumarc7824172018-07-20 14:36:49 +0530195 struct zynq_gpio_platdata *platdata = dev_get_platdata(dev);
Michal Simek615900b2018-06-13 13:22:08 +0200196 u32 bank;
Siva Durga Prasad Paladugu1904ce52016-03-10 16:27:43 +0530197
Vipul Kumarc7824172018-07-20 14:36:49 +0530198 for (bank = 0; bank < platdata->p_data->max_bank; bank++) {
199 if (pin_num >= platdata->p_data->bank_min[bank] &&
200 pin_num <= platdata->p_data->bank_max[bank]) {
201 *bank_num = bank;
202 *bank_pin_num = pin_num -
203 platdata->p_data->bank_min[bank];
204 return;
Siva Durga Prasad Paladugu1904ce52016-03-10 16:27:43 +0530205 }
206 }
207
Vipul Kumarc7824172018-07-20 14:36:49 +0530208 if (bank >= platdata->p_data->max_bank) {
Michal Simekd05b7942018-07-12 12:30:34 +0200209 printf("Invalid bank and pin num\n");
Andrea Scian4bbf3ca2015-03-20 16:00:25 +0100210 *bank_num = 0;
211 *bank_pin_num = 0;
Andrea Scian4bbf3ca2015-03-20 16:00:25 +0100212 }
213}
214
Siva Durga Prasad Paladugu1904ce52016-03-10 16:27:43 +0530215static int gpio_is_valid(unsigned gpio, struct udevice *dev)
Andrea Scian4bbf3ca2015-03-20 16:00:25 +0100216{
Vipul Kumarc7824172018-07-20 14:36:49 +0530217 struct zynq_gpio_platdata *platdata = dev_get_platdata(dev);
Siva Durga Prasad Paladugu1904ce52016-03-10 16:27:43 +0530218
Vipul Kumarc7824172018-07-20 14:36:49 +0530219 return gpio < platdata->p_data->ngpio;
Andrea Scian4bbf3ca2015-03-20 16:00:25 +0100220}
221
Siva Durga Prasad Paladugu1904ce52016-03-10 16:27:43 +0530222static int check_gpio(unsigned gpio, struct udevice *dev)
Andrea Scian4bbf3ca2015-03-20 16:00:25 +0100223{
Siva Durga Prasad Paladugu1904ce52016-03-10 16:27:43 +0530224 if (!gpio_is_valid(gpio, dev)) {
Andrea Scian4bbf3ca2015-03-20 16:00:25 +0100225 printf("ERROR : check_gpio: invalid GPIO %d\n", gpio);
226 return -1;
Andrea Scian4bbf3ca2015-03-20 16:00:25 +0100227 }
Andrea Scian4bbf3ca2015-03-20 16:00:25 +0100228 return 0;
229}
230
Siva Durga Prasad Paladugu6fea9012016-03-10 16:27:38 +0530231static int zynq_gpio_get_value(struct udevice *dev, unsigned gpio)
232{
233 u32 data;
234 unsigned int bank_num, bank_pin_num;
Vipul Kumarc7824172018-07-20 14:36:49 +0530235 struct zynq_gpio_platdata *platdata = dev_get_platdata(dev);
Siva Durga Prasad Paladugu6fea9012016-03-10 16:27:38 +0530236
Siva Durga Prasad Paladugu1904ce52016-03-10 16:27:43 +0530237 if (check_gpio(gpio, dev) < 0)
Siva Durga Prasad Paladugu6fea9012016-03-10 16:27:38 +0530238 return -1;
239
Siva Durga Prasad Paladugu1904ce52016-03-10 16:27:43 +0530240 zynq_gpio_get_bank_pin(gpio, &bank_num, &bank_pin_num, dev);
Siva Durga Prasad Paladugu6fea9012016-03-10 16:27:38 +0530241
Vipul Kumarc7824172018-07-20 14:36:49 +0530242 data = readl(platdata->base +
Siva Durga Prasad Paladugu6fea9012016-03-10 16:27:38 +0530243 ZYNQ_GPIO_DATA_RO_OFFSET(bank_num));
244
245 return (data >> bank_pin_num) & 1;
246}
247
248static int zynq_gpio_set_value(struct udevice *dev, unsigned gpio, int value)
249{
250 unsigned int reg_offset, bank_num, bank_pin_num;
Vipul Kumarc7824172018-07-20 14:36:49 +0530251 struct zynq_gpio_platdata *platdata = dev_get_platdata(dev);
Siva Durga Prasad Paladugu6fea9012016-03-10 16:27:38 +0530252
Siva Durga Prasad Paladugu1904ce52016-03-10 16:27:43 +0530253 if (check_gpio(gpio, dev) < 0)
Siva Durga Prasad Paladugu6fea9012016-03-10 16:27:38 +0530254 return -1;
255
Siva Durga Prasad Paladugu1904ce52016-03-10 16:27:43 +0530256 zynq_gpio_get_bank_pin(gpio, &bank_num, &bank_pin_num, dev);
Siva Durga Prasad Paladugu6fea9012016-03-10 16:27:38 +0530257
258 if (bank_pin_num >= ZYNQ_GPIO_MID_PIN_NUM) {
259 /* only 16 data bits in bit maskable reg */
260 bank_pin_num -= ZYNQ_GPIO_MID_PIN_NUM;
261 reg_offset = ZYNQ_GPIO_DATA_MSW_OFFSET(bank_num);
262 } else {
263 reg_offset = ZYNQ_GPIO_DATA_LSW_OFFSET(bank_num);
264 }
265
266 /*
267 * get the 32 bit value to be written to the mask/data register where
268 * the upper 16 bits is the mask and lower 16 bits is the data
269 */
270 value = !!value;
271 value = ~(1 << (bank_pin_num + ZYNQ_GPIO_MID_PIN_NUM)) &
272 ((value << bank_pin_num) | ZYNQ_GPIO_UPPER_MASK);
273
Vipul Kumarc7824172018-07-20 14:36:49 +0530274 writel(value, platdata->base + reg_offset);
Siva Durga Prasad Paladugu6fea9012016-03-10 16:27:38 +0530275
276 return 0;
277}
278
279static int zynq_gpio_direction_input(struct udevice *dev, unsigned gpio)
280{
281 u32 reg;
282 unsigned int bank_num, bank_pin_num;
Vipul Kumarc7824172018-07-20 14:36:49 +0530283 struct zynq_gpio_platdata *platdata = dev_get_platdata(dev);
Siva Durga Prasad Paladugu6fea9012016-03-10 16:27:38 +0530284
Siva Durga Prasad Paladugu1904ce52016-03-10 16:27:43 +0530285 if (check_gpio(gpio, dev) < 0)
Siva Durga Prasad Paladugu6fea9012016-03-10 16:27:38 +0530286 return -1;
287
Siva Durga Prasad Paladugu1904ce52016-03-10 16:27:43 +0530288 zynq_gpio_get_bank_pin(gpio, &bank_num, &bank_pin_num, dev);
Siva Durga Prasad Paladugu6fea9012016-03-10 16:27:38 +0530289
290 /* bank 0 pins 7 and 8 are special and cannot be used as inputs */
291 if (bank_num == 0 && (bank_pin_num == 7 || bank_pin_num == 8))
292 return -1;
293
294 /* clear the bit in direction mode reg to set the pin as input */
Vipul Kumarc7824172018-07-20 14:36:49 +0530295 reg = readl(platdata->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
Siva Durga Prasad Paladugu6fea9012016-03-10 16:27:38 +0530296 reg &= ~BIT(bank_pin_num);
Vipul Kumarc7824172018-07-20 14:36:49 +0530297 writel(reg, platdata->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
Siva Durga Prasad Paladugu6fea9012016-03-10 16:27:38 +0530298
299 return 0;
300}
301
302static int zynq_gpio_direction_output(struct udevice *dev, unsigned gpio,
303 int value)
304{
305 u32 reg;
306 unsigned int bank_num, bank_pin_num;
Vipul Kumarc7824172018-07-20 14:36:49 +0530307 struct zynq_gpio_platdata *platdata = dev_get_platdata(dev);
Siva Durga Prasad Paladugu6fea9012016-03-10 16:27:38 +0530308
Siva Durga Prasad Paladugu1904ce52016-03-10 16:27:43 +0530309 if (check_gpio(gpio, dev) < 0)
Siva Durga Prasad Paladugu6fea9012016-03-10 16:27:38 +0530310 return -1;
311
Siva Durga Prasad Paladugu1904ce52016-03-10 16:27:43 +0530312 zynq_gpio_get_bank_pin(gpio, &bank_num, &bank_pin_num, dev);
Siva Durga Prasad Paladugu6fea9012016-03-10 16:27:38 +0530313
314 /* set the GPIO pin as output */
Vipul Kumarc7824172018-07-20 14:36:49 +0530315 reg = readl(platdata->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
Siva Durga Prasad Paladugu6fea9012016-03-10 16:27:38 +0530316 reg |= BIT(bank_pin_num);
Vipul Kumarc7824172018-07-20 14:36:49 +0530317 writel(reg, platdata->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
Siva Durga Prasad Paladugu6fea9012016-03-10 16:27:38 +0530318
319 /* configure the output enable reg for the pin */
Vipul Kumarc7824172018-07-20 14:36:49 +0530320 reg = readl(platdata->base + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));
Siva Durga Prasad Paladugu6fea9012016-03-10 16:27:38 +0530321 reg |= BIT(bank_pin_num);
Vipul Kumarc7824172018-07-20 14:36:49 +0530322 writel(reg, platdata->base + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));
Siva Durga Prasad Paladugu6fea9012016-03-10 16:27:38 +0530323
324 /* set the state of the pin */
Ashok Reddy Somafb0f93a2019-09-11 04:40:11 -0600325 zynq_gpio_set_value(dev, gpio, value);
Siva Durga Prasad Paladugu6fea9012016-03-10 16:27:38 +0530326 return 0;
327}
328
Michal Simek514281f2016-03-04 15:56:50 +0100329static int zynq_gpio_get_function(struct udevice *dev, unsigned offset)
330{
331 u32 reg;
332 unsigned int bank_num, bank_pin_num;
Vipul Kumarc7824172018-07-20 14:36:49 +0530333 struct zynq_gpio_platdata *platdata = dev_get_platdata(dev);
Michal Simek514281f2016-03-04 15:56:50 +0100334
335 if (check_gpio(offset, dev) < 0)
336 return -1;
337
338 zynq_gpio_get_bank_pin(offset, &bank_num, &bank_pin_num, dev);
339
340 /* set the GPIO pin as output */
Vipul Kumarc7824172018-07-20 14:36:49 +0530341 reg = readl(platdata->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
Michal Simek514281f2016-03-04 15:56:50 +0100342 reg &= BIT(bank_pin_num);
343 if (reg)
344 return GPIOF_OUTPUT;
345 else
346 return GPIOF_INPUT;
347}
348
Siva Durga Prasad Paladugu6fea9012016-03-10 16:27:38 +0530349static const struct dm_gpio_ops gpio_zynq_ops = {
350 .direction_input = zynq_gpio_direction_input,
351 .direction_output = zynq_gpio_direction_output,
352 .get_value = zynq_gpio_get_value,
353 .set_value = zynq_gpio_set_value,
Michal Simek514281f2016-03-04 15:56:50 +0100354 .get_function = zynq_gpio_get_function,
Siva Durga Prasad Paladugu6fea9012016-03-10 16:27:38 +0530355};
356
Siva Durga Prasad Paladugu1904ce52016-03-10 16:27:43 +0530357static const struct udevice_id zynq_gpio_ids[] = {
358 { .compatible = "xlnx,zynq-gpio-1.0",
359 .data = (ulong)&zynq_gpio_def},
360 { .compatible = "xlnx,zynqmp-gpio-1.0",
361 .data = (ulong)&zynqmp_gpio_def},
Ashok Reddy Somac8a53072019-09-16 03:35:16 -0600362 { .compatible = "xlnx,versal-gpio-1.0",
363 .data = (ulong)&versal_gpio_def},
Shubhrajyoti Datta470e5fb2019-09-18 12:10:31 +0530364 { .compatible = "xlnx,pmc-gpio-1.0",
365 .data = (ulong)&pmc_gpio_def },
Siva Durga Prasad Paladugu1904ce52016-03-10 16:27:43 +0530366 { }
367};
368
Siva Durga Prasad Paladugu6fea9012016-03-10 16:27:38 +0530369static int zynq_gpio_probe(struct udevice *dev)
370{
Vipul Kumarc7824172018-07-20 14:36:49 +0530371 struct zynq_gpio_platdata *platdata = dev_get_platdata(dev);
Siva Durga Prasad Paladugu1904ce52016-03-10 16:27:43 +0530372 struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
Michal Simek305f1c52018-08-02 12:58:54 +0200373 const void *label_ptr;
Siva Durga Prasad Paladugu6fea9012016-03-10 16:27:38 +0530374
Michal Simek305f1c52018-08-02 12:58:54 +0200375 label_ptr = dev_read_prop(dev, "label", NULL);
376 if (label_ptr) {
377 uc_priv->bank_name = strdup(label_ptr);
378 if (!uc_priv->bank_name)
379 return -ENOMEM;
380 } else {
381 uc_priv->bank_name = dev->name;
382 }
Michal Simeke4406652018-06-21 13:58:56 +0200383
Vipul Kumarc7824172018-07-20 14:36:49 +0530384 if (platdata->p_data)
385 uc_priv->gpio_count = platdata->p_data->ngpio;
Siva Durga Prasad Paladugu6fea9012016-03-10 16:27:38 +0530386
387 return 0;
388}
389
390static int zynq_gpio_ofdata_to_platdata(struct udevice *dev)
391{
Vipul Kumarc7824172018-07-20 14:36:49 +0530392 struct zynq_gpio_platdata *platdata = dev_get_platdata(dev);
Siva Durga Prasad Paladugu6fea9012016-03-10 16:27:38 +0530393
Vipul Kumarc7824172018-07-20 14:36:49 +0530394 platdata->base = (phys_addr_t)dev_read_addr(dev);
Siva Durga Prasad Paladugu6fea9012016-03-10 16:27:38 +0530395
Vipul Kumarc7824172018-07-20 14:36:49 +0530396 platdata->p_data =
397 (struct zynq_platform_data *)dev_get_driver_data(dev);
Michal Simek625bc082018-07-12 10:58:04 +0200398
Andrea Scian4bbf3ca2015-03-20 16:00:25 +0100399 return 0;
400}
Siva Durga Prasad Paladugu6fea9012016-03-10 16:27:38 +0530401
Siva Durga Prasad Paladugu6fea9012016-03-10 16:27:38 +0530402U_BOOT_DRIVER(gpio_zynq) = {
403 .name = "gpio_zynq",
404 .id = UCLASS_GPIO,
405 .ops = &gpio_zynq_ops,
406 .of_match = zynq_gpio_ids,
407 .ofdata_to_platdata = zynq_gpio_ofdata_to_platdata,
408 .probe = zynq_gpio_probe,
Vipul Kumarc7824172018-07-20 14:36:49 +0530409 .platdata_auto_alloc_size = sizeof(struct zynq_gpio_platdata),
Siva Durga Prasad Paladugu6fea9012016-03-10 16:27:38 +0530410};