| Mario Six | defed5e | 2018-08-09 14:51:17 +0200 | [diff] [blame] | 1 | gdsys AXI busses of IHS FPGA devices |
| 2 | |
| 3 | Certain gdsys IHS FPGAs offer a interface to their built-in AXI bus with which |
| 4 | the connected devices (usually IP cores) can be controlled via software. |
| 5 | |
| 6 | Required properties: |
| 7 | - compatible: must be "gdsys,ihs_axi" |
| 8 | - reg: describes the address and length of the AXI bus's register map (within |
| 9 | the FPGA's register space) |
| 10 | |
| 11 | Example: |
| 12 | |
| 13 | fpga0_axi_video0 { |
| 14 | #address-cells = <1>; |
| 15 | #size-cells = <1>; |
| 16 | compatible = "gdsys,ihs_axi"; |
| 17 | reg = <0x170 0x10>; |
| 18 | |
| 19 | axi_dev_1 { |
| 20 | ... |
| 21 | }; |
| 22 | }; |