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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Joe Hammane0bdea32007-08-09 15:10:53 -05002/*
3 * Copyright 2007 Wind River Systemes, Inc. <www.windriver.com>
4 * Copyright 2007 Embedded Specialties, Inc.
5 * Joe Hamman joe.hamman@embeddedspecialties.com
6 *
7 * Copyright 2004 Freescale Semiconductor.
8 * Jeff Brown
9 * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
10 *
11 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
Joe Hammane0bdea32007-08-09 15:10:53 -050012 */
13
14#include <common.h>
15#include <command.h>
Simon Glass18afe102019-11-14 12:57:47 -070016#include <init.h>
Joe Hammane0bdea32007-08-09 15:10:53 -050017#include <pci.h>
18#include <asm/processor.h>
19#include <asm/immap_86xx.h>
Kumar Gala9bbd6432009-04-02 13:22:48 -050020#include <asm/fsl_pci.h>
York Sunf0626592013-09-30 09:22:09 -070021#include <fsl_ddr_sdram.h>
Kumar Gala3d020382010-12-15 04:55:20 -060022#include <asm/fsl_serdes.h>
Masahiro Yamada75f82d02018-03-05 01:20:11 +090023#include <linux/libfdt.h>
Jon Loeliger84640c92008-02-18 14:01:56 -060024#include <fdt_support.h>
Joe Hammane0bdea32007-08-09 15:10:53 -050025
Simon Glass39f90ba2017-03-31 08:40:25 -060026DECLARE_GLOBAL_DATA_PTR;
27
Joe Hammane0bdea32007-08-09 15:10:53 -050028long int fixed_sdram (void);
29
30int board_early_init_f (void)
31{
32 return 0;
33}
34
35int checkboard (void)
36{
37 puts ("Board: Wind River SBC8641D\n");
38
Joe Hammane0bdea32007-08-09 15:10:53 -050039 return 0;
40}
41
Simon Glassd35f3382017-04-06 12:47:05 -060042int dram_init(void)
Joe Hammane0bdea32007-08-09 15:10:53 -050043{
44 long dram_size = 0;
45
46#if defined(CONFIG_SPD_EEPROM)
Kumar Galaa7adfe32008-08-26 15:01:37 -050047 dram_size = fsl_ddr_sdram();
Joe Hammane0bdea32007-08-09 15:10:53 -050048#else
49 dram_size = fixed_sdram ();
50#endif
51
Wolfgang Denkf2bbb532011-07-25 10:13:53 +020052 debug (" DDR: ");
Simon Glass39f90ba2017-03-31 08:40:25 -060053 gd->ram_size = dram_size;
54
55 return 0;
Joe Hammane0bdea32007-08-09 15:10:53 -050056}
57
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020058#if defined(CONFIG_SYS_DRAM_TEST)
Joe Hammane0bdea32007-08-09 15:10:53 -050059int testdram (void)
60{
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020061 uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
62 uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
Joe Hammane0bdea32007-08-09 15:10:53 -050063 uint *p;
64
65 puts ("SDRAM test phase 1:\n");
66 for (p = pstart; p < pend; p++)
67 *p = 0xaaaaaaaa;
68
69 for (p = pstart; p < pend; p++) {
70 if (*p != 0xaaaaaaaa) {
71 printf ("SDRAM test fails at: %08x\n", (uint) p);
72 return 1;
73 }
74 }
75
76 puts ("SDRAM test phase 2:\n");
77 for (p = pstart; p < pend; p++)
78 *p = 0x55555555;
79
80 for (p = pstart; p < pend; p++) {
81 if (*p != 0x55555555) {
82 printf ("SDRAM test fails at: %08x\n", (uint) p);
83 return 1;
84 }
85 }
86
87 puts ("SDRAM test passed.\n");
88 return 0;
89}
90#endif
91
92#if !defined(CONFIG_SPD_EEPROM)
93/*
94 * Fixed sdram init -- doesn't use serial presence detect.
95 */
96long int fixed_sdram (void)
97{
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020098#if !defined(CONFIG_SYS_RAMBOOT)
99 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
York Suna21803d2013-11-18 10:29:32 -0800100 volatile struct ccsr_ddr *ddr = &immap->im_ddr1;
Joe Hammane0bdea32007-08-09 15:10:53 -0500101
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200102 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
103 ddr->cs1_bnds = CONFIG_SYS_DDR_CS1_BNDS;
104 ddr->cs2_bnds = CONFIG_SYS_DDR_CS2_BNDS;
105 ddr->cs3_bnds = CONFIG_SYS_DDR_CS3_BNDS;
106 ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
107 ddr->cs1_config = CONFIG_SYS_DDR_CS1_CONFIG;
108 ddr->cs2_config = CONFIG_SYS_DDR_CS2_CONFIG;
109 ddr->cs3_config = CONFIG_SYS_DDR_CS3_CONFIG;
110 ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
111 ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
112 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
113 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
Peter Tyseraf5829cb2009-07-17 10:14:45 -0500114 ddr->sdram_cfg = CONFIG_SYS_DDR_CFG_1A;
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200115 ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CFG_2;
Peter Tyseraf5829cb2009-07-17 10:14:45 -0500116 ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200117 ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
York Suna21803d2013-11-18 10:29:32 -0800118 ddr->sdram_md_cntl = CONFIG_SYS_DDR_MODE_CTL;
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200119 ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
120 ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
121 ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
Joe Hammane0bdea32007-08-09 15:10:53 -0500122
123 asm ("sync;isync");
124
125 udelay (500);
126
Peter Tyseraf5829cb2009-07-17 10:14:45 -0500127 ddr->sdram_cfg = CONFIG_SYS_DDR_CFG_1B;
Joe Hammane0bdea32007-08-09 15:10:53 -0500128 asm ("sync; isync");
129
130 udelay (500);
131 ddr = &immap->im_ddr2;
132
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200133 ddr->cs0_bnds = CONFIG_SYS_DDR2_CS0_BNDS;
134 ddr->cs1_bnds = CONFIG_SYS_DDR2_CS1_BNDS;
135 ddr->cs2_bnds = CONFIG_SYS_DDR2_CS2_BNDS;
136 ddr->cs3_bnds = CONFIG_SYS_DDR2_CS3_BNDS;
137 ddr->cs0_config = CONFIG_SYS_DDR2_CS0_CONFIG;
138 ddr->cs1_config = CONFIG_SYS_DDR2_CS1_CONFIG;
139 ddr->cs2_config = CONFIG_SYS_DDR2_CS2_CONFIG;
140 ddr->cs3_config = CONFIG_SYS_DDR2_CS3_CONFIG;
141 ddr->timing_cfg_3 = CONFIG_SYS_DDR2_EXT_REFRESH;
142 ddr->timing_cfg_0 = CONFIG_SYS_DDR2_TIMING_0;
143 ddr->timing_cfg_1 = CONFIG_SYS_DDR2_TIMING_1;
144 ddr->timing_cfg_2 = CONFIG_SYS_DDR2_TIMING_2;
Peter Tyseraf5829cb2009-07-17 10:14:45 -0500145 ddr->sdram_cfg = CONFIG_SYS_DDR2_CFG_1A;
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200146 ddr->sdram_cfg_2 = CONFIG_SYS_DDR2_CFG_2;
Peter Tyseraf5829cb2009-07-17 10:14:45 -0500147 ddr->sdram_mode = CONFIG_SYS_DDR2_MODE_1;
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200148 ddr->sdram_mode_2 = CONFIG_SYS_DDR2_MODE_2;
York Suna21803d2013-11-18 10:29:32 -0800149 ddr->sdram_md_cntl = CONFIG_SYS_DDR2_MODE_CTL;
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200150 ddr->sdram_interval = CONFIG_SYS_DDR2_INTERVAL;
151 ddr->sdram_data_init = CONFIG_SYS_DDR2_DATA_INIT;
152 ddr->sdram_clk_cntl = CONFIG_SYS_DDR2_CLK_CTRL;
Joe Hammane0bdea32007-08-09 15:10:53 -0500153
154 asm ("sync;isync");
155
156 udelay (500);
157
Peter Tyseraf5829cb2009-07-17 10:14:45 -0500158 ddr->sdram_cfg = CONFIG_SYS_DDR2_CFG_1B;
Joe Hammane0bdea32007-08-09 15:10:53 -0500159 asm ("sync; isync");
160
161 udelay (500);
162#endif
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200163 return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
Joe Hammane0bdea32007-08-09 15:10:53 -0500164}
165#endif /* !defined(CONFIG_SPD_EEPROM) */
166
167#if defined(CONFIG_PCI)
168/*
169 * Initialize PCI Devices, report devices found.
170 */
171
Joe Hamman18f2f032007-08-11 06:54:58 -0500172void pci_init_board(void)
173{
Kumar Galacc8b5342010-12-17 10:26:44 -0600174 fsl_pcie_init_board(0);
Joe Hammane0bdea32007-08-09 15:10:53 -0500175}
Kumar Galacc8b5342010-12-17 10:26:44 -0600176#endif /* CONFIG_PCI */
Joe Hammane0bdea32007-08-09 15:10:53 -0500177
Jon Loeliger84640c92008-02-18 14:01:56 -0600178
179#if defined(CONFIG_OF_BOARD_SETUP)
Simon Glass2aec3cc2014-10-23 18:58:47 -0600180int ft_board_setup(void *blob, bd_t *bd)
Joe Hammane0bdea32007-08-09 15:10:53 -0500181{
Jon Loeliger84640c92008-02-18 14:01:56 -0600182 ft_cpu_setup(blob, bd);
Joe Hammane0bdea32007-08-09 15:10:53 -0500183
Kumar Galad0f27d32010-07-08 22:37:44 -0500184 FT_FSL_PCI_SETUP;
Simon Glass2aec3cc2014-10-23 18:58:47 -0600185
186 return 0;
Joe Hammane0bdea32007-08-09 15:10:53 -0500187}
188#endif
189
190void sbc8641d_reset_board (void)
191{
192 puts ("Resetting board....\n");
193}
194
195/*
196 * get_board_sys_clk
197 * Clock is fixed at 1GHz on this board. Used for CONFIG_SYS_CLK_FREQ
198 */
199
200unsigned long get_board_sys_clk (ulong dummy)
201{
202 int i;
203 ulong val = 0;
204
205 i = 5;
206 i &= 0x07;
207
208 switch (i) {
209 case 0:
210 val = 33000000;
211 break;
212 case 1:
213 val = 40000000;
214 break;
215 case 2:
216 val = 50000000;
217 break;
218 case 3:
219 val = 66000000;
220 break;
221 case 4:
222 val = 83000000;
223 break;
224 case 5:
225 val = 100000000;
226 break;
227 case 6:
228 val = 134000000;
229 break;
230 case 7:
231 val = 166000000;
232 break;
233 }
234
235 return val;
236}
Peter Tyser69454402009-02-05 11:25:25 -0600237
238void board_reset(void)
239{
240#ifdef CONFIG_SYS_RESET_ADDRESS
241 ulong addr = CONFIG_SYS_RESET_ADDRESS;
242
243 /* flush and disable I/D cache */
244 __asm__ __volatile__ ("mfspr 3, 1008" ::: "r3");
245 __asm__ __volatile__ ("ori 5, 5, 0xcc00" ::: "r5");
246 __asm__ __volatile__ ("ori 4, 3, 0xc00" ::: "r4");
247 __asm__ __volatile__ ("andc 5, 3, 5" ::: "r5");
248 __asm__ __volatile__ ("sync");
249 __asm__ __volatile__ ("mtspr 1008, 4");
250 __asm__ __volatile__ ("isync");
251 __asm__ __volatile__ ("sync");
252 __asm__ __volatile__ ("mtspr 1008, 5");
253 __asm__ __volatile__ ("isync");
254 __asm__ __volatile__ ("sync");
255
256 /*
257 * SRR0 has system reset vector, SRR1 has default MSR value
258 * rfi restores MSR from SRR1 and sets the PC to the SRR0 value
259 */
260 __asm__ __volatile__ ("mtspr 26, %0" :: "r" (addr));
261 __asm__ __volatile__ ("li 4, (1 << 6)" ::: "r4");
262 __asm__ __volatile__ ("mtspr 27, 4");
263 __asm__ __volatile__ ("rfi");
264#endif
265}