| Adam Ford | d42247d | 2020-12-11 06:01:46 -0600 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| 2 | /* |
| 3 | * Copyright 2020 Compass Electronics Group, LLC |
| 4 | */ |
| 5 | |
| 6 | #ifndef __IMX8MN_BEACON_H |
| 7 | #define __IMX8MN_BEACON_H |
| 8 | |
| 9 | #include <linux/sizes.h> |
| 10 | #include <asm/arch/imx-regs.h> |
| 11 | |
| Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 12 | #define CFG_SYS_UBOOT_BASE \ |
| Adam Ford | d42247d | 2020-12-11 06:01:46 -0600 | [diff] [blame] | 13 | (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) |
| 14 | |
| Adam Ford | d42247d | 2020-12-11 06:01:46 -0600 | [diff] [blame] | 15 | /* Link Definitions */ |
| Adam Ford | d42247d | 2020-12-11 06:01:46 -0600 | [diff] [blame] | 16 | |
| Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 17 | #define CFG_SYS_INIT_RAM_ADDR 0x40000000 |
| 18 | #define CFG_SYS_INIT_RAM_SIZE 0x200000 |
| Adam Ford | d42247d | 2020-12-11 06:01:46 -0600 | [diff] [blame] | 19 | |
| Tom Rini | bb4dd96 | 2022-11-16 13:10:37 -0500 | [diff] [blame] | 20 | #define CFG_SYS_SDRAM_BASE 0x40000000 |
| Adam Ford | d42247d | 2020-12-11 06:01:46 -0600 | [diff] [blame] | 21 | #define PHYS_SDRAM 0x40000000 |
| Simon Glass | 33ed90a | 2023-02-05 15:40:10 -0700 | [diff] [blame] | 22 | #if IS_ENABLED(CONFIG_IMX8MN_BEACON_2GB_LPDDR) |
| Adam Ford | dd39a6e | 2021-02-16 08:19:52 -0600 | [diff] [blame] | 23 | #define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */ |
| 24 | #else |
| Adam Ford | d42247d | 2020-12-11 06:01:46 -0600 | [diff] [blame] | 25 | #define PHYS_SDRAM_SIZE 0x40000000 /* 1GB DDR */ |
| Adam Ford | dd39a6e | 2021-02-16 08:19:52 -0600 | [diff] [blame] | 26 | #endif |
| Adam Ford | d42247d | 2020-12-11 06:01:46 -0600 | [diff] [blame] | 27 | |
| Adam Ford | d42247d | 2020-12-11 06:01:46 -0600 | [diff] [blame] | 28 | #endif |