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git01.mediatek.com / filogic / uboot / c93b518c6366bef07e1311aef2f01b95f14ef8c8 / . / drivers / clk / sunxi / clk_r40.c
blob: 0fef6f3566d524e172da5fb19e02c1527739af01 [file] [log] [blame]
Jagan Teki66c07fd2018-08-05 11:16:33 +0530[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (C) 2018 Amarula Solutions.
4 * Author: Jagan Teki <jagan@amarulasolutions.com>
5 */
6
7#include <common.h>
8#include <clk-uclass.h>
9#include <dm.h>
10#include <errno.h>
Samuel Holland12e3faa2021-09-12 11:48:43 -0500[diff] [blame]11#include <clk/sunxi.h>
Jagan Teki66c07fd2018-08-05 11:16:33 +0530[diff] [blame]12#include <dt-bindings/clock/sun8i-r40-ccu.h>
13#include <dt-bindings/reset/sun8i-r40-ccu.h>
Simon Glass4dcacfc2020-05-10 11:40:13 -0600[diff] [blame]14#include <linux/bitops.h>
Jagan Teki66c07fd2018-08-05 11:16:33 +0530[diff] [blame]15
16static struct ccu_clk_gate r40_gates[] = {
Samuel Holland1467d442022-11-28 01:02:24 -0600[diff] [blame]17 [CLK_BUS_MIPI_DSI] = GATE(0x060, BIT(1)),
Andre Przywaraddf33c12019-01-29 15:54:09 +0000[diff] [blame]18 [CLK_BUS_MMC0] = GATE(0x060, BIT(8)),
19 [CLK_BUS_MMC1] = GATE(0x060, BIT(9)),
20 [CLK_BUS_MMC2] = GATE(0x060, BIT(10)),
21 [CLK_BUS_MMC3] = GATE(0x060, BIT(11)),
Samuel Hollanda0f27ba2023-01-22 16:06:31 -0600[diff] [blame]22 [CLK_BUS_NAND] = GATE(0x060, BIT(13)),
Jagan Tekibc123132019-02-27 20:02:06 +0530[diff] [blame]23 [CLK_BUS_SPI0] = GATE(0x060, BIT(20)),
24 [CLK_BUS_SPI1] = GATE(0x060, BIT(21)),
25 [CLK_BUS_SPI2] = GATE(0x060, BIT(22)),
26 [CLK_BUS_SPI3] = GATE(0x060, BIT(23)),
Jagan Teki66c07fd2018-08-05 11:16:33 +0530[diff] [blame]27 [CLK_BUS_OTG] = GATE(0x060, BIT(25)),
28 [CLK_BUS_EHCI0] = GATE(0x060, BIT(26)),
29 [CLK_BUS_EHCI1] = GATE(0x060, BIT(27)),
30 [CLK_BUS_EHCI2] = GATE(0x060, BIT(28)),
31 [CLK_BUS_OHCI0] = GATE(0x060, BIT(29)),
32 [CLK_BUS_OHCI1] = GATE(0x060, BIT(30)),
33 [CLK_BUS_OHCI2] = GATE(0x060, BIT(31)),
34
Samuel Holland1467d442022-11-28 01:02:24 -0600[diff] [blame]35 [CLK_BUS_HDMI0] = GATE(0x064, BIT(10)),
36 [CLK_BUS_HDMI1] = GATE(0x064, BIT(11)),
37 [CLK_BUS_DE] = GATE(0x064, BIT(12)),
Jagan Teki836631b2019-02-28 00:26:57 +0530[diff] [blame]38 [CLK_BUS_GMAC] = GATE(0x064, BIT(17)),
Samuel Holland1467d442022-11-28 01:02:24 -0600[diff] [blame]39 [CLK_BUS_TCON_LCD0] = GATE(0x064, BIT(26)),
40 [CLK_BUS_TCON_LCD1] = GATE(0x064, BIT(27)),
41 [CLK_BUS_TCON_TV0] = GATE(0x064, BIT(28)),
42 [CLK_BUS_TCON_TV1] = GATE(0x064, BIT(29)),
43 [CLK_BUS_TCON_TOP] = GATE(0x064, BIT(30)),
Jagan Teki836631b2019-02-28 00:26:57 +0530[diff] [blame]44
Andre Przywara3e9aa0b2022-05-04 22:10:28 +0100[diff] [blame]45 [CLK_BUS_PIO] = GATE(0x068, BIT(5)),
46
Samuel Hollandfa7a7fa2021-09-12 09:47:24 -0500[diff] [blame]47 [CLK_BUS_I2C0] = GATE(0x06c, BIT(0)),
48 [CLK_BUS_I2C1] = GATE(0x06c, BIT(1)),
49 [CLK_BUS_I2C2] = GATE(0x06c, BIT(2)),
50 [CLK_BUS_I2C3] = GATE(0x06c, BIT(3)),
51 [CLK_BUS_I2C4] = GATE(0x06c, BIT(15)),
Jagan Teki8cf08ea2018-12-30 21:29:24 +0530[diff] [blame]52 [CLK_BUS_UART0] = GATE(0x06c, BIT(16)),
53 [CLK_BUS_UART1] = GATE(0x06c, BIT(17)),
54 [CLK_BUS_UART2] = GATE(0x06c, BIT(18)),
55 [CLK_BUS_UART3] = GATE(0x06c, BIT(19)),
56 [CLK_BUS_UART4] = GATE(0x06c, BIT(20)),
57 [CLK_BUS_UART5] = GATE(0x06c, BIT(21)),
58 [CLK_BUS_UART6] = GATE(0x06c, BIT(22)),
59 [CLK_BUS_UART7] = GATE(0x06c, BIT(23)),
60
Samuel Hollanda0f27ba2023-01-22 16:06:31 -0600[diff] [blame]61 [CLK_NAND] = GATE(0x080, BIT(31)),
Jagan Tekibc123132019-02-27 20:02:06 +0530[diff] [blame]62 [CLK_SPI0] = GATE(0x0a0, BIT(31)),
63 [CLK_SPI1] = GATE(0x0a4, BIT(31)),
64 [CLK_SPI2] = GATE(0x0a8, BIT(31)),
65 [CLK_SPI3] = GATE(0x0ac, BIT(31)),
66
Jagan Teki66c07fd2018-08-05 11:16:33 +0530[diff] [blame]67 [CLK_USB_PHY0] = GATE(0x0cc, BIT(8)),
68 [CLK_USB_PHY1] = GATE(0x0cc, BIT(9)),
69 [CLK_USB_PHY2] = GATE(0x0cc, BIT(10)),
70 [CLK_USB_OHCI0] = GATE(0x0cc, BIT(16)),
71 [CLK_USB_OHCI1] = GATE(0x0cc, BIT(17)),
72 [CLK_USB_OHCI2] = GATE(0x0cc, BIT(18)),
Samuel Holland1467d442022-11-28 01:02:24 -0600[diff] [blame]73
74 [CLK_DE] = GATE(0x104, BIT(31)),
75 [CLK_TCON_LCD0] = GATE(0x110, BIT(31)),
76 [CLK_TCON_LCD1] = GATE(0x114, BIT(31)),
77 [CLK_TCON_TV0] = GATE(0x118, BIT(31)),
78 [CLK_TCON_TV1] = GATE(0x11c, BIT(31)),
79
80 [CLK_HDMI] = GATE(0x150, BIT(31)),
81 [CLK_HDMI_SLOW] = GATE(0x154, BIT(31)),
82
83 [CLK_DSI_DPHY] = GATE(0x168, BIT(15)),
Jagan Teki66c07fd2018-08-05 11:16:33 +0530[diff] [blame]84};
85
86static struct ccu_reset r40_resets[] = {
87 [RST_USB_PHY0] = RESET(0x0cc, BIT(0)),
88 [RST_USB_PHY1] = RESET(0x0cc, BIT(1)),
89 [RST_USB_PHY2] = RESET(0x0cc, BIT(2)),
90
Samuel Holland1467d442022-11-28 01:02:24 -0600[diff] [blame]91 [RST_BUS_MIPI_DSI] = RESET(0x2c0, BIT(1)),
Andre Przywaraddf33c12019-01-29 15:54:09 +0000[diff] [blame]92 [RST_BUS_MMC0] = RESET(0x2c0, BIT(8)),
93 [RST_BUS_MMC1] = RESET(0x2c0, BIT(9)),
94 [RST_BUS_MMC2] = RESET(0x2c0, BIT(10)),
95 [RST_BUS_MMC3] = RESET(0x2c0, BIT(11)),
Samuel Hollanda0f27ba2023-01-22 16:06:31 -0600[diff] [blame]96 [RST_BUS_NAND] = RESET(0x2c0, BIT(13)),
Jagan Tekibc123132019-02-27 20:02:06 +0530[diff] [blame]97 [RST_BUS_SPI0] = RESET(0x2c0, BIT(20)),
98 [RST_BUS_SPI1] = RESET(0x2c0, BIT(21)),
99 [RST_BUS_SPI2] = RESET(0x2c0, BIT(22)),
100 [RST_BUS_SPI3] = RESET(0x2c0, BIT(23)),
Jagan Teki66c07fd2018-08-05 11:16:33 +0530[diff] [blame]101 [RST_BUS_OTG] = RESET(0x2c0, BIT(25)),
102 [RST_BUS_EHCI0] = RESET(0x2c0, BIT(26)),
103 [RST_BUS_EHCI1] = RESET(0x2c0, BIT(27)),
104 [RST_BUS_EHCI2] = RESET(0x2c0, BIT(28)),
105 [RST_BUS_OHCI0] = RESET(0x2c0, BIT(29)),
106 [RST_BUS_OHCI1] = RESET(0x2c0, BIT(30)),
107 [RST_BUS_OHCI2] = RESET(0x2c0, BIT(31)),
Jagan Tekib490aa52018-12-30 21:37:31 +0530[diff] [blame]108
Samuel Holland1467d442022-11-28 01:02:24 -0600[diff] [blame]109 [RST_BUS_HDMI0] = RESET(0x2c4, BIT(10)),
110 [RST_BUS_HDMI1] = RESET(0x2c4, BIT(11)),
111 [RST_BUS_DE] = RESET(0x2c4, BIT(12)),
Jagan Tekifc228202019-04-15 16:42:16 +0530[diff] [blame]112 [RST_BUS_GMAC] = RESET(0x2c4, BIT(17)),
Samuel Holland1467d442022-11-28 01:02:24 -0600[diff] [blame]113 [RST_BUS_TCON_LCD0] = RESET(0x2c4, BIT(26)),
114 [RST_BUS_TCON_LCD1] = RESET(0x2c4, BIT(27)),
115 [RST_BUS_TCON_TV0] = RESET(0x2c4, BIT(28)),
116 [RST_BUS_TCON_TV1] = RESET(0x2c4, BIT(29)),
117 [RST_BUS_TCON_TOP] = RESET(0x2c4, BIT(30)),
Jagan Tekifc228202019-04-15 16:42:16 +0530[diff] [blame]118
Samuel Hollandfa7a7fa2021-09-12 09:47:24 -0500[diff] [blame]119 [RST_BUS_I2C0] = RESET(0x2d8, BIT(0)),
120 [RST_BUS_I2C1] = RESET(0x2d8, BIT(1)),
121 [RST_BUS_I2C2] = RESET(0x2d8, BIT(2)),
122 [RST_BUS_I2C3] = RESET(0x2d8, BIT(3)),
123 [RST_BUS_I2C4] = RESET(0x2d8, BIT(15)),
Jagan Tekib490aa52018-12-30 21:37:31 +0530[diff] [blame]124 [RST_BUS_UART0] = RESET(0x2d8, BIT(16)),
125 [RST_BUS_UART1] = RESET(0x2d8, BIT(17)),
126 [RST_BUS_UART2] = RESET(0x2d8, BIT(18)),
127 [RST_BUS_UART3] = RESET(0x2d8, BIT(19)),
128 [RST_BUS_UART4] = RESET(0x2d8, BIT(20)),
129 [RST_BUS_UART5] = RESET(0x2d8, BIT(21)),
130 [RST_BUS_UART6] = RESET(0x2d8, BIT(22)),
131 [RST_BUS_UART7] = RESET(0x2d8, BIT(23)),
Jagan Teki66c07fd2018-08-05 11:16:33 +0530[diff] [blame]132};
133
Samuel Holland751c6c62022-05-09 00:29:34 -0500[diff] [blame]134const struct ccu_desc r40_ccu_desc = {
Jagan Teki66c07fd2018-08-05 11:16:33 +0530[diff] [blame]135 .gates = r40_gates,
136 .resets = r40_resets,
Samuel Holland84436502022-05-09 00:29:31 -0500[diff] [blame]137 .num_gates = ARRAY_SIZE(r40_gates),
138 .num_resets = ARRAY_SIZE(r40_resets),
Jagan Teki66c07fd2018-08-05 11:16:33 +0530[diff] [blame]139};