Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / c8cdce758cc266f92c15bda7e456bdd0294a1b63 / . / include / configs / sama5d4ek.h
blob: aa8573d8ba02455e2626caf08d45aa79c203f0f9 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
Bo Shen58645902014-11-10 15:24:02 +0800[diff] [blame]2/*
3 * Configuration settings for the SAMA5D4EK board.
4 *
5 * Copyright (C) 2014 Atmel
6 * Bo Shen <voice.shen@atmel.com>
Bo Shen58645902014-11-10 15:24:02 +0800[diff] [blame]7 */
8
9#ifndef __CONFIG_H
10#define __CONFIG_H
11
Wu, Josh42587542015-03-30 14:51:19 +0800[diff] [blame]12#include "at91-sama5_common.h"
Bo Shen58645902014-11-10 15:24:02 +0800[diff] [blame]13
Bo Shen58645902014-11-10 15:24:02 +0800[diff] [blame]14/* SDRAM */
Wenyou Yangd19b9012017-09-14 11:07:42 +0800[diff] [blame]15#define CONFIG_SYS_SDRAM_BASE 0x20000000
Bo Shen58645902014-11-10 15:24:02 +0800[diff] [blame]16#define CONFIG_SYS_SDRAM_SIZE 0x20000000
17
Bo Shen05f95632014-12-15 13:24:38 +0800[diff] [blame]18#ifdef CONFIG_SPL_BUILD
Wenyou Yang9673c2e2017-04-13 10:31:19 +0800[diff] [blame]19#define CONFIG_SYS_INIT_SP_ADDR 0x218000
Bo Shen05f95632014-12-15 13:24:38 +0800[diff] [blame]20#else
Bo Shen58645902014-11-10 15:24:02 +0800[diff] [blame]21#define CONFIG_SYS_INIT_SP_ADDR \
Wenyou Yang9673c2e2017-04-13 10:31:19 +0800[diff] [blame]22 (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
Bo Shen05f95632014-12-15 13:24:38 +0800[diff] [blame]23#endif
Bo Shen58645902014-11-10 15:24:02 +0800[diff] [blame]24
25#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
26
Bo Shen58645902014-11-10 15:24:02 +0800[diff] [blame]27#ifdef CONFIG_CMD_SF
Bo Shen58645902014-11-10 15:24:02 +0800[diff] [blame]28#define CONFIG_SF_DEFAULT_SPEED 30000000
29#endif
30
31/* NAND flash */
Bo Shen58645902014-11-10 15:24:02 +0800[diff] [blame]32#ifdef CONFIG_CMD_NAND
Bo Shen58645902014-11-10 15:24:02 +0800[diff] [blame]33#define CONFIG_SYS_MAX_NAND_DEVICE 1
Wenyou Yangd19b9012017-09-14 11:07:42 +0800[diff] [blame]34#define CONFIG_SYS_NAND_BASE 0x80000000
Bo Shen58645902014-11-10 15:24:02 +0800[diff] [blame]35/* our ALE is AD21 */
36#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
37/* our CLE is AD22 */
38#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
39#define CONFIG_SYS_NAND_ONFI_DETECTION
40/* PMECC & PMERRLOC */
41#define CONFIG_ATMEL_NAND_HWECC
42#define CONFIG_ATMEL_NAND_HW_PMECC
43#endif
44
Bo Shen05f95632014-12-15 13:24:38 +0800[diff] [blame]45/* SPL */
Bo Shen05f95632014-12-15 13:24:38 +0800[diff] [blame]46#define CONFIG_SPL_TEXT_BASE 0x200000
Wenyou Yang9673c2e2017-04-13 10:31:19 +0800[diff] [blame]47#define CONFIG_SPL_MAX_SIZE 0x18000
Bo Shen05f95632014-12-15 13:24:38 +0800[diff] [blame]48#define CONFIG_SPL_BSS_START_ADDR 0x20000000
49#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
50#define CONFIG_SYS_SPL_MALLOC_START 0x20080000
51#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
52
Bo Shen05f95632014-12-15 13:24:38 +0800[diff] [blame]53#define CONFIG_SYS_MONITOR_LEN (512 << 10)
54
Wenyou Yange035ea72017-09-14 11:07:44 +0800[diff] [blame]55#ifdef CONFIG_SD_BOOT
Bo Shen05f95632014-12-15 13:24:38 +0800[diff] [blame]56#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
57#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
Bo Shen05f95632014-12-15 13:24:38 +0800[diff] [blame]58
Wenyou Yange035ea72017-09-14 11:07:44 +0800[diff] [blame]59#elif CONFIG_SPI_BOOT
Wenyou Yange035ea72017-09-14 11:07:44 +0800[diff] [blame]60#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x10000
61
62#elif CONFIG_NAND_BOOT
Bo Shen05f95632014-12-15 13:24:38 +0800[diff] [blame]63#define CONFIG_SPL_NAND_DRIVERS
64#define CONFIG_SPL_NAND_BASE
Wenyou Yange035ea72017-09-14 11:07:44 +0800[diff] [blame]65#endif
Bo Shen05f95632014-12-15 13:24:38 +0800[diff] [blame]66#define CONFIG_PMECC_CAP 8
67#define CONFIG_PMECC_SECTOR_SIZE 512
68#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
69#define CONFIG_SYS_NAND_5_ADDR_CYCLE
70#define CONFIG_SYS_NAND_PAGE_SIZE 0x1000
71#define CONFIG_SYS_NAND_PAGE_COUNT 64
72#define CONFIG_SYS_NAND_OOBSIZE 224
73#define CONFIG_SYS_NAND_BLOCK_SIZE 0x40000
74#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0
75#define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER
76
Bo Shen58645902014-11-10 15:24:02 +0800[diff] [blame]77#endif