blob: f2fcb3927cbbb323f30c69468c8aaf687b390f06 [file] [log] [blame]
Simon Glass791f61b2012-12-03 13:56:51 +00001/dts-v1/;
2
Stephen Warren3f972cc2013-07-24 10:09:20 -07003/include/ "coreboot.dtsi"
Simon Glass791f61b2012-12-03 13:56:51 +00004
5/ {
Wolfgang Denkec7fbf52013-10-04 17:43:24 +02006 #address-cells = <1>;
7 #size-cells = <1>;
Simon Glass791f61b2012-12-03 13:56:51 +00008 model = "Google Link";
9 compatible = "google,link", "intel,celeron-ivybridge";
10
11 config {
12 silent_console = <0>;
13 };
14
Simon Glass1fad1462014-10-10 07:49:19 -060015 gpioa {
16 compatible = "intel,ich6-gpio";
17 reg = <0 0x10>;
18 bank-name = "A";
19 };
20
21 gpiob {
22 compatible = "intel,ich6-gpio";
23 reg = <0x30 0x10>;
24 bank-name = "B";
25 };
26
27 gpioc {
28 compatible = "intel,ich6-gpio";
29 reg = <0x40 0x10>;
30 bank-name = "C";
31 };
Simon Glass791f61b2012-12-03 13:56:51 +000032
33 serial {
34 reg = <0x3f8 8>;
35 clock-frequency = <115200>;
36 };
37
Wolfgang Denkec7fbf52013-10-04 17:43:24 +020038 chosen { };
39 memory { device_type = "memory"; reg = <0 0>; };
Simon Glass87323ed2013-03-11 06:08:10 +000040
41 spi {
42 #address-cells = <1>;
43 #size-cells = <0>;
44 compatible = "intel,ich9";
45 spi-flash@0 {
46 reg = <0>;
47 compatible = "winbond,w25q64", "spi-flash";
48 memory-map = <0xff800000 0x00800000>;
49 };
50 };
Simon Glasse4e56272014-10-10 07:30:13 -060051
52 lpc {
53 compatible = "intel,lpc";
54 #address-cells = <1>;
55 #size-cells = <1>;
56 cros-ec@200 {
57 compatible = "google,cros-ec";
58 reg = <0x204 1 0x200 1 0x880 0x80>;
59
60 /* This describes the flash memory within the EC */
61 #address-cells = <1>;
62 #size-cells = <1>;
63 flash@8000000 {
64 reg = <0x08000000 0x20000>;
65 erase-value = <0xff>;
66 };
67 };
68 };
Simon Glass791f61b2012-12-03 13:56:51 +000069};