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git01.mediatek.com / filogic / uboot / c8c200933756d3fc2be9d866e98716a456dadb02 / . / arch / arm / dts / dra7-evm-u-boot.dtsi
blob: 3fe1fb4552df313906fa71b1f86bb5f3d13f8985 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
Jean-Jacques Hiblot0296b602017-09-15 12:39:41 +0200[diff] [blame]2/*
Nishanth Menoneaa39c62023-11-01 15:56:03 -0500[diff] [blame]3 * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
Jean-Jacques Hiblot0296b602017-09-15 12:39:41 +0200[diff] [blame]4 */
5
6#include "omap5-u-boot.dtsi"
7
8&pcf_gpio_21{
9 u-boot,i2c-offset-len = <0>;
10};
11
12&pcf_hdmi{
13 u-boot,i2c-offset-len = <0>;
14};
Jean-Jacques Hiblota45f72d2018-02-27 17:05:50 +0100[diff] [blame]15
16&mmc2_pins_default {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]17 bootph-pre-ram;
Jean-Jacques Hiblota45f72d2018-02-27 17:05:50 +0100[diff] [blame]18};
19
20&mmc2_pins_hs {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]21 bootph-pre-ram;
Jean-Jacques Hiblota45f72d2018-02-27 17:05:50 +0100[diff] [blame]22};
23
24&mmc2_pins_ddr_rev20 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]25 bootph-pre-ram;
Jean-Jacques Hiblota45f72d2018-02-27 17:05:50 +0100[diff] [blame]26};
27
28&mmc2_pins_hs200 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]29 bootph-pre-ram;
Jean-Jacques Hiblota45f72d2018-02-27 17:05:50 +0100[diff] [blame]30};
31
32&mmc2_iodelay_hs200_rev20_conf {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]33 bootph-pre-ram;
Jean-Jacques Hiblota45f72d2018-02-27 17:05:50 +0100[diff] [blame]34};
Faiz Abbase220a462019-10-09 12:35:18 +0200[diff] [blame]35
36&omap_dwc3_1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]37 bootph-pre-ram;
Faiz Abbase220a462019-10-09 12:35:18 +0200[diff] [blame]38};
39
40&usb1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]41 bootph-pre-ram;
Faiz Abbase220a462019-10-09 12:35:18 +0200[diff] [blame]42 dr_mode = "peripheral";
43};
44
45&usb2_phy1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]46 bootph-pre-ram;
Faiz Abbase220a462019-10-09 12:35:18 +0200[diff] [blame]47};
48
49&usb3_phy1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]50 bootph-pre-ram;
Faiz Abbase220a462019-10-09 12:35:18 +0200[diff] [blame]51};