blob: 77b87e0365be110beef432eb608d375fa2dc51b1 [file] [log] [blame]
Jaehoon Chung7cf73072012-10-15 19:10:29 +00001/*
2 * (C) Copyright 2012 SAMSUNG Electronics
3 * Jaehoon Chung <jh80.chung@samsung.com>
4 * Rajeshawari Shinde <rajeshwari.s@samsung.com>
5 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02006 * SPDX-License-Identifier: GPL-2.0+
Jaehoon Chung7cf73072012-10-15 19:10:29 +00007 */
8
Alexey Brodkin55bab5e2013-12-26 15:29:07 +04009#include <bouncebuf.h>
Jaehoon Chung7cf73072012-10-15 19:10:29 +000010#include <common.h>
Simon Glass4c9b9482015-08-06 20:16:27 -060011#include <errno.h>
Jaehoon Chung7cf73072012-10-15 19:10:29 +000012#include <malloc.h>
13#include <mmc.h>
14#include <dwmmc.h>
Jaehoon Chung7cf73072012-10-15 19:10:29 +000015#include <asm-generic/errno.h>
16
17#define PAGE_SIZE 4096
18
19static int dwmci_wait_reset(struct dwmci_host *host, u32 value)
20{
21 unsigned long timeout = 1000;
22 u32 ctrl;
23
24 dwmci_writel(host, DWMCI_CTRL, value);
25
26 while (timeout--) {
27 ctrl = dwmci_readl(host, DWMCI_CTRL);
28 if (!(ctrl & DWMCI_RESET_ALL))
29 return 1;
30 }
31 return 0;
32}
33
34static void dwmci_set_idma_desc(struct dwmci_idmac *idmac,
35 u32 desc0, u32 desc1, u32 desc2)
36{
37 struct dwmci_idmac *desc = idmac;
38
39 desc->flags = desc0;
40 desc->cnt = desc1;
41 desc->addr = desc2;
42 desc->next_addr = (unsigned int)desc + sizeof(struct dwmci_idmac);
43}
44
45static void dwmci_prepare_data(struct dwmci_host *host,
Alexey Brodkin55bab5e2013-12-26 15:29:07 +040046 struct mmc_data *data,
47 struct dwmci_idmac *cur_idmac,
48 void *bounce_buffer)
Jaehoon Chung7cf73072012-10-15 19:10:29 +000049{
50 unsigned long ctrl;
51 unsigned int i = 0, flags, cnt, blk_cnt;
Alexey Brodkin55bab5e2013-12-26 15:29:07 +040052 ulong data_start, data_end;
Jaehoon Chung7cf73072012-10-15 19:10:29 +000053
54
55 blk_cnt = data->blocks;
56
57 dwmci_wait_reset(host, DWMCI_CTRL_FIFO_RESET);
58
59 data_start = (ulong)cur_idmac;
60 dwmci_writel(host, DWMCI_DBADDR, (unsigned int)cur_idmac);
61
Jaehoon Chung7cf73072012-10-15 19:10:29 +000062 do {
63 flags = DWMCI_IDMAC_OWN | DWMCI_IDMAC_CH ;
64 flags |= (i == 0) ? DWMCI_IDMAC_FS : 0;
65 if (blk_cnt <= 8) {
66 flags |= DWMCI_IDMAC_LD;
67 cnt = data->blocksize * blk_cnt;
68 } else
69 cnt = data->blocksize * 8;
70
71 dwmci_set_idma_desc(cur_idmac, flags, cnt,
Alexey Brodkin55bab5e2013-12-26 15:29:07 +040072 (u32)bounce_buffer + (i * PAGE_SIZE));
Jaehoon Chung7cf73072012-10-15 19:10:29 +000073
Mischa Jonkera7a60912013-07-26 16:18:40 +020074 if (blk_cnt <= 8)
Jaehoon Chung7cf73072012-10-15 19:10:29 +000075 break;
76 blk_cnt -= 8;
77 cur_idmac++;
78 i++;
79 } while(1);
80
81 data_end = (ulong)cur_idmac;
82 flush_dcache_range(data_start, data_end + ARCH_DMA_MINALIGN);
83
84 ctrl = dwmci_readl(host, DWMCI_CTRL);
85 ctrl |= DWMCI_IDMAC_EN | DWMCI_DMA_EN;
86 dwmci_writel(host, DWMCI_CTRL, ctrl);
87
88 ctrl = dwmci_readl(host, DWMCI_BMOD);
89 ctrl |= DWMCI_BMOD_IDMAC_FB | DWMCI_BMOD_IDMAC_EN;
90 dwmci_writel(host, DWMCI_BMOD, ctrl);
91
92 dwmci_writel(host, DWMCI_BLKSIZ, data->blocksize);
93 dwmci_writel(host, DWMCI_BYTCNT, data->blocksize * data->blocks);
94}
95
96static int dwmci_set_transfer_mode(struct dwmci_host *host,
97 struct mmc_data *data)
98{
99 unsigned long mode;
100
101 mode = DWMCI_CMD_DATA_EXP;
102 if (data->flags & MMC_DATA_WRITE)
103 mode |= DWMCI_CMD_RW;
104
105 return mode;
106}
107
108static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
109 struct mmc_data *data)
110{
Pantelis Antoniou2c850462014-03-11 19:34:20 +0200111 struct dwmci_host *host = mmc->priv;
Mischa Jonker7423bed2013-07-26 14:08:14 +0200112 ALLOC_CACHE_ALIGN_BUFFER(struct dwmci_idmac, cur_idmac,
Mischa Jonkera7a60912013-07-26 16:18:40 +0200113 data ? DIV_ROUND_UP(data->blocks, 8) : 0);
Marek Vasut81e093f2015-07-27 22:39:38 +0200114 int ret = 0, flags = 0, i;
Jaehoon Chung7cf73072012-10-15 19:10:29 +0000115 unsigned int timeout = 100000;
116 u32 retry = 10000;
117 u32 mask, ctrl;
Amar902664c2013-04-27 11:42:54 +0530118 ulong start = get_timer(0);
Alexey Brodkin55bab5e2013-12-26 15:29:07 +0400119 struct bounce_buffer bbstate;
Jaehoon Chung7cf73072012-10-15 19:10:29 +0000120
121 while (dwmci_readl(host, DWMCI_STATUS) & DWMCI_BUSY) {
Amar902664c2013-04-27 11:42:54 +0530122 if (get_timer(start) > timeout) {
Simon Glass4c9b9482015-08-06 20:16:27 -0600123 debug("%s: Timeout on data busy\n", __func__);
Jaehoon Chung7cf73072012-10-15 19:10:29 +0000124 return TIMEOUT;
125 }
Jaehoon Chung7cf73072012-10-15 19:10:29 +0000126 }
127
128 dwmci_writel(host, DWMCI_RINTSTS, DWMCI_INTMSK_ALL);
129
Alexey Brodkin55bab5e2013-12-26 15:29:07 +0400130 if (data) {
131 if (data->flags == MMC_DATA_READ) {
132 bounce_buffer_start(&bbstate, (void*)data->dest,
133 data->blocksize *
134 data->blocks, GEN_BB_WRITE);
135 } else {
136 bounce_buffer_start(&bbstate, (void*)data->src,
137 data->blocksize *
138 data->blocks, GEN_BB_READ);
139 }
140 dwmci_prepare_data(host, data, cur_idmac,
141 bbstate.bounce_buffer);
142 }
Jaehoon Chung7cf73072012-10-15 19:10:29 +0000143
Jaehoon Chung7cf73072012-10-15 19:10:29 +0000144 dwmci_writel(host, DWMCI_CMDARG, cmd->cmdarg);
145
146 if (data)
147 flags = dwmci_set_transfer_mode(host, data);
148
149 if ((cmd->resp_type & MMC_RSP_136) && (cmd->resp_type & MMC_RSP_BUSY))
150 return -1;
151
152 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
153 flags |= DWMCI_CMD_ABORT_STOP;
154 else
155 flags |= DWMCI_CMD_PRV_DAT_WAIT;
156
157 if (cmd->resp_type & MMC_RSP_PRESENT) {
158 flags |= DWMCI_CMD_RESP_EXP;
159 if (cmd->resp_type & MMC_RSP_136)
160 flags |= DWMCI_CMD_RESP_LENGTH;
161 }
162
163 if (cmd->resp_type & MMC_RSP_CRC)
164 flags |= DWMCI_CMD_CHECK_CRC;
165
166 flags |= (cmd->cmdidx | DWMCI_CMD_START | DWMCI_CMD_USE_HOLD_REG);
167
168 debug("Sending CMD%d\n",cmd->cmdidx);
169
170 dwmci_writel(host, DWMCI_CMD, flags);
171
172 for (i = 0; i < retry; i++) {
173 mask = dwmci_readl(host, DWMCI_RINTSTS);
174 if (mask & DWMCI_INTMSK_CDONE) {
175 if (!data)
176 dwmci_writel(host, DWMCI_RINTSTS, mask);
177 break;
178 }
179 }
180
Pavel Macheka425f5d2014-09-05 12:49:48 +0200181 if (i == retry) {
Simon Glass4c9b9482015-08-06 20:16:27 -0600182 debug("%s: Timeout.\n", __func__);
Jaehoon Chung7cf73072012-10-15 19:10:29 +0000183 return TIMEOUT;
Pavel Macheka425f5d2014-09-05 12:49:48 +0200184 }
Jaehoon Chung7cf73072012-10-15 19:10:29 +0000185
186 if (mask & DWMCI_INTMSK_RTO) {
Pavel Macheka425f5d2014-09-05 12:49:48 +0200187 /*
188 * Timeout here is not necessarily fatal. (e)MMC cards
189 * will splat here when they receive CMD55 as they do
190 * not support this command and that is exactly the way
191 * to tell them apart from SD cards. Thus, this output
192 * below shall be debug(). eMMC cards also do not favor
193 * CMD8, please keep that in mind.
194 */
195 debug("%s: Response Timeout.\n", __func__);
Jaehoon Chung7cf73072012-10-15 19:10:29 +0000196 return TIMEOUT;
197 } else if (mask & DWMCI_INTMSK_RE) {
Simon Glass4c9b9482015-08-06 20:16:27 -0600198 debug("%s: Response Error.\n", __func__);
199 return -EIO;
Jaehoon Chung7cf73072012-10-15 19:10:29 +0000200 }
201
202
203 if (cmd->resp_type & MMC_RSP_PRESENT) {
204 if (cmd->resp_type & MMC_RSP_136) {
205 cmd->response[0] = dwmci_readl(host, DWMCI_RESP3);
206 cmd->response[1] = dwmci_readl(host, DWMCI_RESP2);
207 cmd->response[2] = dwmci_readl(host, DWMCI_RESP1);
208 cmd->response[3] = dwmci_readl(host, DWMCI_RESP0);
209 } else {
210 cmd->response[0] = dwmci_readl(host, DWMCI_RESP0);
211 }
212 }
213
214 if (data) {
Marek Vasut795de7b2015-07-27 22:39:37 +0200215 start = get_timer(0);
216 timeout = 1000;
217 for (;;) {
Jaehoon Chung7cf73072012-10-15 19:10:29 +0000218 mask = dwmci_readl(host, DWMCI_RINTSTS);
Marek Vasut795de7b2015-07-27 22:39:37 +0200219 /* Error during data transfer. */
Jaehoon Chung7cf73072012-10-15 19:10:29 +0000220 if (mask & (DWMCI_DATA_ERR | DWMCI_DATA_TOUT)) {
Simon Glass4c9b9482015-08-06 20:16:27 -0600221 debug("%s: DATA ERROR!\n", __func__);
Marek Vasut81e093f2015-07-27 22:39:38 +0200222 ret = -EINVAL;
223 break;
Jaehoon Chung7cf73072012-10-15 19:10:29 +0000224 }
Marek Vasut795de7b2015-07-27 22:39:37 +0200225
226 /* Data arrived correctly. */
Marek Vasut81e093f2015-07-27 22:39:38 +0200227 if (mask & DWMCI_INTMSK_DTO) {
228 ret = 0;
Marek Vasut795de7b2015-07-27 22:39:37 +0200229 break;
Marek Vasut81e093f2015-07-27 22:39:38 +0200230 }
Marek Vasut795de7b2015-07-27 22:39:37 +0200231
232 /* Check for timeout. */
233 if (get_timer(start) > timeout) {
Simon Glass4c9b9482015-08-06 20:16:27 -0600234 debug("%s: Timeout waiting for data!\n",
Marek Vasut795de7b2015-07-27 22:39:37 +0200235 __func__);
Marek Vasut81e093f2015-07-27 22:39:38 +0200236 ret = TIMEOUT;
237 break;
Marek Vasut795de7b2015-07-27 22:39:37 +0200238 }
239 }
Jaehoon Chung7cf73072012-10-15 19:10:29 +0000240
241 dwmci_writel(host, DWMCI_RINTSTS, mask);
242
243 ctrl = dwmci_readl(host, DWMCI_CTRL);
244 ctrl &= ~(DWMCI_DMA_EN);
245 dwmci_writel(host, DWMCI_CTRL, ctrl);
Alexey Brodkin55bab5e2013-12-26 15:29:07 +0400246
247 bounce_buffer_stop(&bbstate);
Jaehoon Chung7cf73072012-10-15 19:10:29 +0000248 }
249
250 udelay(100);
251
Marek Vasut81e093f2015-07-27 22:39:38 +0200252 return ret;
Jaehoon Chung7cf73072012-10-15 19:10:29 +0000253}
254
255static int dwmci_setup_bus(struct dwmci_host *host, u32 freq)
256{
257 u32 div, status;
258 int timeout = 10000;
259 unsigned long sclk;
260
Amar902664c2013-04-27 11:42:54 +0530261 if ((freq == host->clock) || (freq == 0))
Jaehoon Chung7cf73072012-10-15 19:10:29 +0000262 return 0;
Jaehoon Chung7cf73072012-10-15 19:10:29 +0000263 /*
Pavel Macheka425f5d2014-09-05 12:49:48 +0200264 * If host->get_mmc_clk isn't defined,
Jaehoon Chung7cf73072012-10-15 19:10:29 +0000265 * then assume that host->bus_hz is source clock value.
Pavel Macheka425f5d2014-09-05 12:49:48 +0200266 * host->bus_hz should be set by user.
Jaehoon Chung7cf73072012-10-15 19:10:29 +0000267 */
Jaehoon Chungd94735b2013-10-06 18:59:31 +0900268 if (host->get_mmc_clk)
Rajeshwari S Shindeccfa20b2014-02-05 10:48:15 +0530269 sclk = host->get_mmc_clk(host);
Jaehoon Chung7cf73072012-10-15 19:10:29 +0000270 else if (host->bus_hz)
271 sclk = host->bus_hz;
272 else {
Simon Glass4c9b9482015-08-06 20:16:27 -0600273 debug("%s: Didn't get source clock value.\n", __func__);
Jaehoon Chung7cf73072012-10-15 19:10:29 +0000274 return -EINVAL;
275 }
276
Chin Liang See4cfff952014-06-10 01:26:52 -0500277 if (sclk == freq)
278 div = 0; /* bypass mode */
279 else
280 div = DIV_ROUND_UP(sclk, 2 * freq);
Jaehoon Chung7cf73072012-10-15 19:10:29 +0000281
282 dwmci_writel(host, DWMCI_CLKENA, 0);
283 dwmci_writel(host, DWMCI_CLKSRC, 0);
284
285 dwmci_writel(host, DWMCI_CLKDIV, div);
286 dwmci_writel(host, DWMCI_CMD, DWMCI_CMD_PRV_DAT_WAIT |
287 DWMCI_CMD_UPD_CLK | DWMCI_CMD_START);
288
289 do {
290 status = dwmci_readl(host, DWMCI_CMD);
291 if (timeout-- < 0) {
Simon Glass4c9b9482015-08-06 20:16:27 -0600292 debug("%s: Timeout!\n", __func__);
Jaehoon Chung7cf73072012-10-15 19:10:29 +0000293 return -ETIMEDOUT;
294 }
295 } while (status & DWMCI_CMD_START);
296
297 dwmci_writel(host, DWMCI_CLKENA, DWMCI_CLKEN_ENABLE |
298 DWMCI_CLKEN_LOW_PWR);
299
300 dwmci_writel(host, DWMCI_CMD, DWMCI_CMD_PRV_DAT_WAIT |
301 DWMCI_CMD_UPD_CLK | DWMCI_CMD_START);
302
303 timeout = 10000;
304 do {
305 status = dwmci_readl(host, DWMCI_CMD);
306 if (timeout-- < 0) {
Simon Glass4c9b9482015-08-06 20:16:27 -0600307 debug("%s: Timeout!\n", __func__);
Jaehoon Chung7cf73072012-10-15 19:10:29 +0000308 return -ETIMEDOUT;
309 }
310 } while (status & DWMCI_CMD_START);
311
312 host->clock = freq;
313
314 return 0;
315}
316
317static void dwmci_set_ios(struct mmc *mmc)
318{
Jaehoon Chunge8672942014-05-16 13:59:55 +0900319 struct dwmci_host *host = (struct dwmci_host *)mmc->priv;
320 u32 ctype, regs;
Jaehoon Chung7cf73072012-10-15 19:10:29 +0000321
Pavel Macheka425f5d2014-09-05 12:49:48 +0200322 debug("Buswidth = %d, clock: %d\n", mmc->bus_width, mmc->clock);
Jaehoon Chung7cf73072012-10-15 19:10:29 +0000323
324 dwmci_setup_bus(host, mmc->clock);
325 switch (mmc->bus_width) {
326 case 8:
327 ctype = DWMCI_CTYPE_8BIT;
328 break;
329 case 4:
330 ctype = DWMCI_CTYPE_4BIT;
331 break;
332 default:
333 ctype = DWMCI_CTYPE_1BIT;
334 break;
335 }
336
337 dwmci_writel(host, DWMCI_CTYPE, ctype);
338
Jaehoon Chunge8672942014-05-16 13:59:55 +0900339 regs = dwmci_readl(host, DWMCI_UHS_REG);
Andrew Gabbasov54c0e222014-12-01 06:59:12 -0600340 if (mmc->ddr_mode)
Jaehoon Chunge8672942014-05-16 13:59:55 +0900341 regs |= DWMCI_DDR_MODE;
342 else
Jaehoon Chung401fc502015-01-14 17:37:53 +0900343 regs &= ~DWMCI_DDR_MODE;
Jaehoon Chunge8672942014-05-16 13:59:55 +0900344
345 dwmci_writel(host, DWMCI_UHS_REG, regs);
346
Jaehoon Chung7cf73072012-10-15 19:10:29 +0000347 if (host->clksel)
348 host->clksel(host);
349}
350
351static int dwmci_init(struct mmc *mmc)
352{
Pantelis Antoniou2c850462014-03-11 19:34:20 +0200353 struct dwmci_host *host = mmc->priv;
Jaehoon Chung7cf73072012-10-15 19:10:29 +0000354
Jaehoon Chung42f81a82013-11-29 20:08:57 +0900355 if (host->board_init)
356 host->board_init(host);
Rajeshwari Shinde70163092013-10-29 12:53:13 +0530357
Jaehoon Chung7cf73072012-10-15 19:10:29 +0000358 dwmci_writel(host, DWMCI_PWREN, 1);
359
360 if (!dwmci_wait_reset(host, DWMCI_RESET_ALL)) {
Simon Glass4c9b9482015-08-06 20:16:27 -0600361 debug("%s[%d] Fail-reset!!\n", __func__, __LINE__);
362 return -EIO;
Jaehoon Chung7cf73072012-10-15 19:10:29 +0000363 }
364
Amar902664c2013-04-27 11:42:54 +0530365 /* Enumerate at 400KHz */
Pantelis Antoniou2c850462014-03-11 19:34:20 +0200366 dwmci_setup_bus(host, mmc->cfg->f_min);
Amar902664c2013-04-27 11:42:54 +0530367
Jaehoon Chung7cf73072012-10-15 19:10:29 +0000368 dwmci_writel(host, DWMCI_RINTSTS, 0xFFFFFFFF);
369 dwmci_writel(host, DWMCI_INTMASK, 0);
370
371 dwmci_writel(host, DWMCI_TMOUT, 0xFFFFFFFF);
372
373 dwmci_writel(host, DWMCI_IDINTEN, 0);
374 dwmci_writel(host, DWMCI_BMOD, 1);
375
Simon Glass6133efa2015-08-06 20:16:29 -0600376 if (!host->fifoth_val) {
377 uint32_t fifo_size;
378
379 fifo_size = dwmci_readl(host, DWMCI_FIFOTH);
380 fifo_size = ((fifo_size & RX_WMARK_MASK) >> RX_WMARK_SHIFT) + 1;
381 host->fifoth_val = MSIZE(0x2) | RX_WMARK(fifo_size / 2 - 1) |
382 TX_WMARK(fifo_size / 2);
Amar902664c2013-04-27 11:42:54 +0530383 }
Simon Glass6133efa2015-08-06 20:16:29 -0600384 dwmci_writel(host, DWMCI_FIFOTH, host->fifoth_val);
Jaehoon Chung7cf73072012-10-15 19:10:29 +0000385
386 dwmci_writel(host, DWMCI_CLKENA, 0);
387 dwmci_writel(host, DWMCI_CLKSRC, 0);
388
389 return 0;
390}
391
Pantelis Antoniouc9e75912014-02-26 19:28:45 +0200392static const struct mmc_ops dwmci_ops = {
393 .send_cmd = dwmci_send_cmd,
394 .set_ios = dwmci_set_ios,
395 .init = dwmci_init,
396};
397
Jaehoon Chung7cf73072012-10-15 19:10:29 +0000398int add_dwmci(struct dwmci_host *host, u32 max_clk, u32 min_clk)
399{
Pantelis Antoniou2c850462014-03-11 19:34:20 +0200400 host->cfg.name = host->name;
401 host->cfg.ops = &dwmci_ops;
402 host->cfg.f_min = min_clk;
403 host->cfg.f_max = max_clk;
Jaehoon Chung7cf73072012-10-15 19:10:29 +0000404
Pantelis Antoniou2c850462014-03-11 19:34:20 +0200405 host->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
Jaehoon Chung7cf73072012-10-15 19:10:29 +0000406
Pantelis Antoniou2c850462014-03-11 19:34:20 +0200407 host->cfg.host_caps = host->caps;
Jaehoon Chung7cf73072012-10-15 19:10:29 +0000408
409 if (host->buswidth == 8) {
Pantelis Antoniou2c850462014-03-11 19:34:20 +0200410 host->cfg.host_caps |= MMC_MODE_8BIT;
411 host->cfg.host_caps &= ~MMC_MODE_4BIT;
Jaehoon Chung7cf73072012-10-15 19:10:29 +0000412 } else {
Pantelis Antoniou2c850462014-03-11 19:34:20 +0200413 host->cfg.host_caps |= MMC_MODE_4BIT;
414 host->cfg.host_caps &= ~MMC_MODE_8BIT;
Jaehoon Chung7cf73072012-10-15 19:10:29 +0000415 }
Rob Herring5fd3edd2015-03-23 17:56:59 -0500416 host->cfg.host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz;
Pantelis Antoniou2c850462014-03-11 19:34:20 +0200417
418 host->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
Jaehoon Chung7cf73072012-10-15 19:10:29 +0000419
Pantelis Antoniou2c850462014-03-11 19:34:20 +0200420 host->mmc = mmc_create(&host->cfg, host);
421 if (host->mmc == NULL)
422 return -1;
Jaehoon Chung7cf73072012-10-15 19:10:29 +0000423
Pantelis Antoniou2c850462014-03-11 19:34:20 +0200424 return 0;
Jaehoon Chung7cf73072012-10-15 19:10:29 +0000425}