Jaehoon Chung | 7cf7307 | 2012-10-15 19:10:29 +0000 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2012 SAMSUNG Electronics |
| 3 | * Jaehoon Chung <jh80.chung@samsung.com> |
| 4 | * Rajeshawari Shinde <rajeshwari.s@samsung.com> |
| 5 | * |
Wolfgang Denk | d79de1d | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 6 | * SPDX-License-Identifier: GPL-2.0+ |
Jaehoon Chung | 7cf7307 | 2012-10-15 19:10:29 +0000 | [diff] [blame] | 7 | */ |
| 8 | |
Alexey Brodkin | 55bab5e | 2013-12-26 15:29:07 +0400 | [diff] [blame] | 9 | #include <bouncebuf.h> |
Jaehoon Chung | 7cf7307 | 2012-10-15 19:10:29 +0000 | [diff] [blame] | 10 | #include <common.h> |
Simon Glass | 4c9b948 | 2015-08-06 20:16:27 -0600 | [diff] [blame] | 11 | #include <errno.h> |
Jaehoon Chung | 7cf7307 | 2012-10-15 19:10:29 +0000 | [diff] [blame] | 12 | #include <malloc.h> |
| 13 | #include <mmc.h> |
| 14 | #include <dwmmc.h> |
Jaehoon Chung | 7cf7307 | 2012-10-15 19:10:29 +0000 | [diff] [blame] | 15 | #include <asm-generic/errno.h> |
| 16 | |
| 17 | #define PAGE_SIZE 4096 |
| 18 | |
| 19 | static int dwmci_wait_reset(struct dwmci_host *host, u32 value) |
| 20 | { |
| 21 | unsigned long timeout = 1000; |
| 22 | u32 ctrl; |
| 23 | |
| 24 | dwmci_writel(host, DWMCI_CTRL, value); |
| 25 | |
| 26 | while (timeout--) { |
| 27 | ctrl = dwmci_readl(host, DWMCI_CTRL); |
| 28 | if (!(ctrl & DWMCI_RESET_ALL)) |
| 29 | return 1; |
| 30 | } |
| 31 | return 0; |
| 32 | } |
| 33 | |
| 34 | static void dwmci_set_idma_desc(struct dwmci_idmac *idmac, |
| 35 | u32 desc0, u32 desc1, u32 desc2) |
| 36 | { |
| 37 | struct dwmci_idmac *desc = idmac; |
| 38 | |
| 39 | desc->flags = desc0; |
| 40 | desc->cnt = desc1; |
| 41 | desc->addr = desc2; |
| 42 | desc->next_addr = (unsigned int)desc + sizeof(struct dwmci_idmac); |
| 43 | } |
| 44 | |
| 45 | static void dwmci_prepare_data(struct dwmci_host *host, |
Alexey Brodkin | 55bab5e | 2013-12-26 15:29:07 +0400 | [diff] [blame] | 46 | struct mmc_data *data, |
| 47 | struct dwmci_idmac *cur_idmac, |
| 48 | void *bounce_buffer) |
Jaehoon Chung | 7cf7307 | 2012-10-15 19:10:29 +0000 | [diff] [blame] | 49 | { |
| 50 | unsigned long ctrl; |
| 51 | unsigned int i = 0, flags, cnt, blk_cnt; |
Alexey Brodkin | 55bab5e | 2013-12-26 15:29:07 +0400 | [diff] [blame] | 52 | ulong data_start, data_end; |
Jaehoon Chung | 7cf7307 | 2012-10-15 19:10:29 +0000 | [diff] [blame] | 53 | |
| 54 | |
| 55 | blk_cnt = data->blocks; |
| 56 | |
| 57 | dwmci_wait_reset(host, DWMCI_CTRL_FIFO_RESET); |
| 58 | |
| 59 | data_start = (ulong)cur_idmac; |
| 60 | dwmci_writel(host, DWMCI_DBADDR, (unsigned int)cur_idmac); |
| 61 | |
Jaehoon Chung | 7cf7307 | 2012-10-15 19:10:29 +0000 | [diff] [blame] | 62 | do { |
| 63 | flags = DWMCI_IDMAC_OWN | DWMCI_IDMAC_CH ; |
| 64 | flags |= (i == 0) ? DWMCI_IDMAC_FS : 0; |
| 65 | if (blk_cnt <= 8) { |
| 66 | flags |= DWMCI_IDMAC_LD; |
| 67 | cnt = data->blocksize * blk_cnt; |
| 68 | } else |
| 69 | cnt = data->blocksize * 8; |
| 70 | |
| 71 | dwmci_set_idma_desc(cur_idmac, flags, cnt, |
Alexey Brodkin | 55bab5e | 2013-12-26 15:29:07 +0400 | [diff] [blame] | 72 | (u32)bounce_buffer + (i * PAGE_SIZE)); |
Jaehoon Chung | 7cf7307 | 2012-10-15 19:10:29 +0000 | [diff] [blame] | 73 | |
Mischa Jonker | a7a6091 | 2013-07-26 16:18:40 +0200 | [diff] [blame] | 74 | if (blk_cnt <= 8) |
Jaehoon Chung | 7cf7307 | 2012-10-15 19:10:29 +0000 | [diff] [blame] | 75 | break; |
| 76 | blk_cnt -= 8; |
| 77 | cur_idmac++; |
| 78 | i++; |
| 79 | } while(1); |
| 80 | |
| 81 | data_end = (ulong)cur_idmac; |
| 82 | flush_dcache_range(data_start, data_end + ARCH_DMA_MINALIGN); |
| 83 | |
| 84 | ctrl = dwmci_readl(host, DWMCI_CTRL); |
| 85 | ctrl |= DWMCI_IDMAC_EN | DWMCI_DMA_EN; |
| 86 | dwmci_writel(host, DWMCI_CTRL, ctrl); |
| 87 | |
| 88 | ctrl = dwmci_readl(host, DWMCI_BMOD); |
| 89 | ctrl |= DWMCI_BMOD_IDMAC_FB | DWMCI_BMOD_IDMAC_EN; |
| 90 | dwmci_writel(host, DWMCI_BMOD, ctrl); |
| 91 | |
| 92 | dwmci_writel(host, DWMCI_BLKSIZ, data->blocksize); |
| 93 | dwmci_writel(host, DWMCI_BYTCNT, data->blocksize * data->blocks); |
| 94 | } |
| 95 | |
| 96 | static int dwmci_set_transfer_mode(struct dwmci_host *host, |
| 97 | struct mmc_data *data) |
| 98 | { |
| 99 | unsigned long mode; |
| 100 | |
| 101 | mode = DWMCI_CMD_DATA_EXP; |
| 102 | if (data->flags & MMC_DATA_WRITE) |
| 103 | mode |= DWMCI_CMD_RW; |
| 104 | |
| 105 | return mode; |
| 106 | } |
| 107 | |
| 108 | static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, |
| 109 | struct mmc_data *data) |
| 110 | { |
Pantelis Antoniou | 2c85046 | 2014-03-11 19:34:20 +0200 | [diff] [blame] | 111 | struct dwmci_host *host = mmc->priv; |
Mischa Jonker | 7423bed | 2013-07-26 14:08:14 +0200 | [diff] [blame] | 112 | ALLOC_CACHE_ALIGN_BUFFER(struct dwmci_idmac, cur_idmac, |
Mischa Jonker | a7a6091 | 2013-07-26 16:18:40 +0200 | [diff] [blame] | 113 | data ? DIV_ROUND_UP(data->blocks, 8) : 0); |
Marek Vasut | 81e093f | 2015-07-27 22:39:38 +0200 | [diff] [blame] | 114 | int ret = 0, flags = 0, i; |
Jaehoon Chung | 7cf7307 | 2012-10-15 19:10:29 +0000 | [diff] [blame] | 115 | unsigned int timeout = 100000; |
| 116 | u32 retry = 10000; |
| 117 | u32 mask, ctrl; |
Amar | 902664c | 2013-04-27 11:42:54 +0530 | [diff] [blame] | 118 | ulong start = get_timer(0); |
Alexey Brodkin | 55bab5e | 2013-12-26 15:29:07 +0400 | [diff] [blame] | 119 | struct bounce_buffer bbstate; |
Jaehoon Chung | 7cf7307 | 2012-10-15 19:10:29 +0000 | [diff] [blame] | 120 | |
| 121 | while (dwmci_readl(host, DWMCI_STATUS) & DWMCI_BUSY) { |
Amar | 902664c | 2013-04-27 11:42:54 +0530 | [diff] [blame] | 122 | if (get_timer(start) > timeout) { |
Simon Glass | 4c9b948 | 2015-08-06 20:16:27 -0600 | [diff] [blame] | 123 | debug("%s: Timeout on data busy\n", __func__); |
Jaehoon Chung | 7cf7307 | 2012-10-15 19:10:29 +0000 | [diff] [blame] | 124 | return TIMEOUT; |
| 125 | } |
Jaehoon Chung | 7cf7307 | 2012-10-15 19:10:29 +0000 | [diff] [blame] | 126 | } |
| 127 | |
| 128 | dwmci_writel(host, DWMCI_RINTSTS, DWMCI_INTMSK_ALL); |
| 129 | |
Alexey Brodkin | 55bab5e | 2013-12-26 15:29:07 +0400 | [diff] [blame] | 130 | if (data) { |
| 131 | if (data->flags == MMC_DATA_READ) { |
| 132 | bounce_buffer_start(&bbstate, (void*)data->dest, |
| 133 | data->blocksize * |
| 134 | data->blocks, GEN_BB_WRITE); |
| 135 | } else { |
| 136 | bounce_buffer_start(&bbstate, (void*)data->src, |
| 137 | data->blocksize * |
| 138 | data->blocks, GEN_BB_READ); |
| 139 | } |
| 140 | dwmci_prepare_data(host, data, cur_idmac, |
| 141 | bbstate.bounce_buffer); |
| 142 | } |
Jaehoon Chung | 7cf7307 | 2012-10-15 19:10:29 +0000 | [diff] [blame] | 143 | |
Jaehoon Chung | 7cf7307 | 2012-10-15 19:10:29 +0000 | [diff] [blame] | 144 | dwmci_writel(host, DWMCI_CMDARG, cmd->cmdarg); |
| 145 | |
| 146 | if (data) |
| 147 | flags = dwmci_set_transfer_mode(host, data); |
| 148 | |
| 149 | if ((cmd->resp_type & MMC_RSP_136) && (cmd->resp_type & MMC_RSP_BUSY)) |
| 150 | return -1; |
| 151 | |
| 152 | if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) |
| 153 | flags |= DWMCI_CMD_ABORT_STOP; |
| 154 | else |
| 155 | flags |= DWMCI_CMD_PRV_DAT_WAIT; |
| 156 | |
| 157 | if (cmd->resp_type & MMC_RSP_PRESENT) { |
| 158 | flags |= DWMCI_CMD_RESP_EXP; |
| 159 | if (cmd->resp_type & MMC_RSP_136) |
| 160 | flags |= DWMCI_CMD_RESP_LENGTH; |
| 161 | } |
| 162 | |
| 163 | if (cmd->resp_type & MMC_RSP_CRC) |
| 164 | flags |= DWMCI_CMD_CHECK_CRC; |
| 165 | |
| 166 | flags |= (cmd->cmdidx | DWMCI_CMD_START | DWMCI_CMD_USE_HOLD_REG); |
| 167 | |
| 168 | debug("Sending CMD%d\n",cmd->cmdidx); |
| 169 | |
| 170 | dwmci_writel(host, DWMCI_CMD, flags); |
| 171 | |
| 172 | for (i = 0; i < retry; i++) { |
| 173 | mask = dwmci_readl(host, DWMCI_RINTSTS); |
| 174 | if (mask & DWMCI_INTMSK_CDONE) { |
| 175 | if (!data) |
| 176 | dwmci_writel(host, DWMCI_RINTSTS, mask); |
| 177 | break; |
| 178 | } |
| 179 | } |
| 180 | |
Pavel Machek | a425f5d | 2014-09-05 12:49:48 +0200 | [diff] [blame] | 181 | if (i == retry) { |
Simon Glass | 4c9b948 | 2015-08-06 20:16:27 -0600 | [diff] [blame] | 182 | debug("%s: Timeout.\n", __func__); |
Jaehoon Chung | 7cf7307 | 2012-10-15 19:10:29 +0000 | [diff] [blame] | 183 | return TIMEOUT; |
Pavel Machek | a425f5d | 2014-09-05 12:49:48 +0200 | [diff] [blame] | 184 | } |
Jaehoon Chung | 7cf7307 | 2012-10-15 19:10:29 +0000 | [diff] [blame] | 185 | |
| 186 | if (mask & DWMCI_INTMSK_RTO) { |
Pavel Machek | a425f5d | 2014-09-05 12:49:48 +0200 | [diff] [blame] | 187 | /* |
| 188 | * Timeout here is not necessarily fatal. (e)MMC cards |
| 189 | * will splat here when they receive CMD55 as they do |
| 190 | * not support this command and that is exactly the way |
| 191 | * to tell them apart from SD cards. Thus, this output |
| 192 | * below shall be debug(). eMMC cards also do not favor |
| 193 | * CMD8, please keep that in mind. |
| 194 | */ |
| 195 | debug("%s: Response Timeout.\n", __func__); |
Jaehoon Chung | 7cf7307 | 2012-10-15 19:10:29 +0000 | [diff] [blame] | 196 | return TIMEOUT; |
| 197 | } else if (mask & DWMCI_INTMSK_RE) { |
Simon Glass | 4c9b948 | 2015-08-06 20:16:27 -0600 | [diff] [blame] | 198 | debug("%s: Response Error.\n", __func__); |
| 199 | return -EIO; |
Jaehoon Chung | 7cf7307 | 2012-10-15 19:10:29 +0000 | [diff] [blame] | 200 | } |
| 201 | |
| 202 | |
| 203 | if (cmd->resp_type & MMC_RSP_PRESENT) { |
| 204 | if (cmd->resp_type & MMC_RSP_136) { |
| 205 | cmd->response[0] = dwmci_readl(host, DWMCI_RESP3); |
| 206 | cmd->response[1] = dwmci_readl(host, DWMCI_RESP2); |
| 207 | cmd->response[2] = dwmci_readl(host, DWMCI_RESP1); |
| 208 | cmd->response[3] = dwmci_readl(host, DWMCI_RESP0); |
| 209 | } else { |
| 210 | cmd->response[0] = dwmci_readl(host, DWMCI_RESP0); |
| 211 | } |
| 212 | } |
| 213 | |
| 214 | if (data) { |
Marek Vasut | 795de7b | 2015-07-27 22:39:37 +0200 | [diff] [blame] | 215 | start = get_timer(0); |
| 216 | timeout = 1000; |
| 217 | for (;;) { |
Jaehoon Chung | 7cf7307 | 2012-10-15 19:10:29 +0000 | [diff] [blame] | 218 | mask = dwmci_readl(host, DWMCI_RINTSTS); |
Marek Vasut | 795de7b | 2015-07-27 22:39:37 +0200 | [diff] [blame] | 219 | /* Error during data transfer. */ |
Jaehoon Chung | 7cf7307 | 2012-10-15 19:10:29 +0000 | [diff] [blame] | 220 | if (mask & (DWMCI_DATA_ERR | DWMCI_DATA_TOUT)) { |
Simon Glass | 4c9b948 | 2015-08-06 20:16:27 -0600 | [diff] [blame] | 221 | debug("%s: DATA ERROR!\n", __func__); |
Marek Vasut | 81e093f | 2015-07-27 22:39:38 +0200 | [diff] [blame] | 222 | ret = -EINVAL; |
| 223 | break; |
Jaehoon Chung | 7cf7307 | 2012-10-15 19:10:29 +0000 | [diff] [blame] | 224 | } |
Marek Vasut | 795de7b | 2015-07-27 22:39:37 +0200 | [diff] [blame] | 225 | |
| 226 | /* Data arrived correctly. */ |
Marek Vasut | 81e093f | 2015-07-27 22:39:38 +0200 | [diff] [blame] | 227 | if (mask & DWMCI_INTMSK_DTO) { |
| 228 | ret = 0; |
Marek Vasut | 795de7b | 2015-07-27 22:39:37 +0200 | [diff] [blame] | 229 | break; |
Marek Vasut | 81e093f | 2015-07-27 22:39:38 +0200 | [diff] [blame] | 230 | } |
Marek Vasut | 795de7b | 2015-07-27 22:39:37 +0200 | [diff] [blame] | 231 | |
| 232 | /* Check for timeout. */ |
| 233 | if (get_timer(start) > timeout) { |
Simon Glass | 4c9b948 | 2015-08-06 20:16:27 -0600 | [diff] [blame] | 234 | debug("%s: Timeout waiting for data!\n", |
Marek Vasut | 795de7b | 2015-07-27 22:39:37 +0200 | [diff] [blame] | 235 | __func__); |
Marek Vasut | 81e093f | 2015-07-27 22:39:38 +0200 | [diff] [blame] | 236 | ret = TIMEOUT; |
| 237 | break; |
Marek Vasut | 795de7b | 2015-07-27 22:39:37 +0200 | [diff] [blame] | 238 | } |
| 239 | } |
Jaehoon Chung | 7cf7307 | 2012-10-15 19:10:29 +0000 | [diff] [blame] | 240 | |
| 241 | dwmci_writel(host, DWMCI_RINTSTS, mask); |
| 242 | |
| 243 | ctrl = dwmci_readl(host, DWMCI_CTRL); |
| 244 | ctrl &= ~(DWMCI_DMA_EN); |
| 245 | dwmci_writel(host, DWMCI_CTRL, ctrl); |
Alexey Brodkin | 55bab5e | 2013-12-26 15:29:07 +0400 | [diff] [blame] | 246 | |
| 247 | bounce_buffer_stop(&bbstate); |
Jaehoon Chung | 7cf7307 | 2012-10-15 19:10:29 +0000 | [diff] [blame] | 248 | } |
| 249 | |
| 250 | udelay(100); |
| 251 | |
Marek Vasut | 81e093f | 2015-07-27 22:39:38 +0200 | [diff] [blame] | 252 | return ret; |
Jaehoon Chung | 7cf7307 | 2012-10-15 19:10:29 +0000 | [diff] [blame] | 253 | } |
| 254 | |
| 255 | static int dwmci_setup_bus(struct dwmci_host *host, u32 freq) |
| 256 | { |
| 257 | u32 div, status; |
| 258 | int timeout = 10000; |
| 259 | unsigned long sclk; |
| 260 | |
Amar | 902664c | 2013-04-27 11:42:54 +0530 | [diff] [blame] | 261 | if ((freq == host->clock) || (freq == 0)) |
Jaehoon Chung | 7cf7307 | 2012-10-15 19:10:29 +0000 | [diff] [blame] | 262 | return 0; |
Jaehoon Chung | 7cf7307 | 2012-10-15 19:10:29 +0000 | [diff] [blame] | 263 | /* |
Pavel Machek | a425f5d | 2014-09-05 12:49:48 +0200 | [diff] [blame] | 264 | * If host->get_mmc_clk isn't defined, |
Jaehoon Chung | 7cf7307 | 2012-10-15 19:10:29 +0000 | [diff] [blame] | 265 | * then assume that host->bus_hz is source clock value. |
Pavel Machek | a425f5d | 2014-09-05 12:49:48 +0200 | [diff] [blame] | 266 | * host->bus_hz should be set by user. |
Jaehoon Chung | 7cf7307 | 2012-10-15 19:10:29 +0000 | [diff] [blame] | 267 | */ |
Jaehoon Chung | d94735b | 2013-10-06 18:59:31 +0900 | [diff] [blame] | 268 | if (host->get_mmc_clk) |
Rajeshwari S Shinde | ccfa20b | 2014-02-05 10:48:15 +0530 | [diff] [blame] | 269 | sclk = host->get_mmc_clk(host); |
Jaehoon Chung | 7cf7307 | 2012-10-15 19:10:29 +0000 | [diff] [blame] | 270 | else if (host->bus_hz) |
| 271 | sclk = host->bus_hz; |
| 272 | else { |
Simon Glass | 4c9b948 | 2015-08-06 20:16:27 -0600 | [diff] [blame] | 273 | debug("%s: Didn't get source clock value.\n", __func__); |
Jaehoon Chung | 7cf7307 | 2012-10-15 19:10:29 +0000 | [diff] [blame] | 274 | return -EINVAL; |
| 275 | } |
| 276 | |
Chin Liang See | 4cfff95 | 2014-06-10 01:26:52 -0500 | [diff] [blame] | 277 | if (sclk == freq) |
| 278 | div = 0; /* bypass mode */ |
| 279 | else |
| 280 | div = DIV_ROUND_UP(sclk, 2 * freq); |
Jaehoon Chung | 7cf7307 | 2012-10-15 19:10:29 +0000 | [diff] [blame] | 281 | |
| 282 | dwmci_writel(host, DWMCI_CLKENA, 0); |
| 283 | dwmci_writel(host, DWMCI_CLKSRC, 0); |
| 284 | |
| 285 | dwmci_writel(host, DWMCI_CLKDIV, div); |
| 286 | dwmci_writel(host, DWMCI_CMD, DWMCI_CMD_PRV_DAT_WAIT | |
| 287 | DWMCI_CMD_UPD_CLK | DWMCI_CMD_START); |
| 288 | |
| 289 | do { |
| 290 | status = dwmci_readl(host, DWMCI_CMD); |
| 291 | if (timeout-- < 0) { |
Simon Glass | 4c9b948 | 2015-08-06 20:16:27 -0600 | [diff] [blame] | 292 | debug("%s: Timeout!\n", __func__); |
Jaehoon Chung | 7cf7307 | 2012-10-15 19:10:29 +0000 | [diff] [blame] | 293 | return -ETIMEDOUT; |
| 294 | } |
| 295 | } while (status & DWMCI_CMD_START); |
| 296 | |
| 297 | dwmci_writel(host, DWMCI_CLKENA, DWMCI_CLKEN_ENABLE | |
| 298 | DWMCI_CLKEN_LOW_PWR); |
| 299 | |
| 300 | dwmci_writel(host, DWMCI_CMD, DWMCI_CMD_PRV_DAT_WAIT | |
| 301 | DWMCI_CMD_UPD_CLK | DWMCI_CMD_START); |
| 302 | |
| 303 | timeout = 10000; |
| 304 | do { |
| 305 | status = dwmci_readl(host, DWMCI_CMD); |
| 306 | if (timeout-- < 0) { |
Simon Glass | 4c9b948 | 2015-08-06 20:16:27 -0600 | [diff] [blame] | 307 | debug("%s: Timeout!\n", __func__); |
Jaehoon Chung | 7cf7307 | 2012-10-15 19:10:29 +0000 | [diff] [blame] | 308 | return -ETIMEDOUT; |
| 309 | } |
| 310 | } while (status & DWMCI_CMD_START); |
| 311 | |
| 312 | host->clock = freq; |
| 313 | |
| 314 | return 0; |
| 315 | } |
| 316 | |
| 317 | static void dwmci_set_ios(struct mmc *mmc) |
| 318 | { |
Jaehoon Chung | e867294 | 2014-05-16 13:59:55 +0900 | [diff] [blame] | 319 | struct dwmci_host *host = (struct dwmci_host *)mmc->priv; |
| 320 | u32 ctype, regs; |
Jaehoon Chung | 7cf7307 | 2012-10-15 19:10:29 +0000 | [diff] [blame] | 321 | |
Pavel Machek | a425f5d | 2014-09-05 12:49:48 +0200 | [diff] [blame] | 322 | debug("Buswidth = %d, clock: %d\n", mmc->bus_width, mmc->clock); |
Jaehoon Chung | 7cf7307 | 2012-10-15 19:10:29 +0000 | [diff] [blame] | 323 | |
| 324 | dwmci_setup_bus(host, mmc->clock); |
| 325 | switch (mmc->bus_width) { |
| 326 | case 8: |
| 327 | ctype = DWMCI_CTYPE_8BIT; |
| 328 | break; |
| 329 | case 4: |
| 330 | ctype = DWMCI_CTYPE_4BIT; |
| 331 | break; |
| 332 | default: |
| 333 | ctype = DWMCI_CTYPE_1BIT; |
| 334 | break; |
| 335 | } |
| 336 | |
| 337 | dwmci_writel(host, DWMCI_CTYPE, ctype); |
| 338 | |
Jaehoon Chung | e867294 | 2014-05-16 13:59:55 +0900 | [diff] [blame] | 339 | regs = dwmci_readl(host, DWMCI_UHS_REG); |
Andrew Gabbasov | 54c0e22 | 2014-12-01 06:59:12 -0600 | [diff] [blame] | 340 | if (mmc->ddr_mode) |
Jaehoon Chung | e867294 | 2014-05-16 13:59:55 +0900 | [diff] [blame] | 341 | regs |= DWMCI_DDR_MODE; |
| 342 | else |
Jaehoon Chung | 401fc50 | 2015-01-14 17:37:53 +0900 | [diff] [blame] | 343 | regs &= ~DWMCI_DDR_MODE; |
Jaehoon Chung | e867294 | 2014-05-16 13:59:55 +0900 | [diff] [blame] | 344 | |
| 345 | dwmci_writel(host, DWMCI_UHS_REG, regs); |
| 346 | |
Jaehoon Chung | 7cf7307 | 2012-10-15 19:10:29 +0000 | [diff] [blame] | 347 | if (host->clksel) |
| 348 | host->clksel(host); |
| 349 | } |
| 350 | |
| 351 | static int dwmci_init(struct mmc *mmc) |
| 352 | { |
Pantelis Antoniou | 2c85046 | 2014-03-11 19:34:20 +0200 | [diff] [blame] | 353 | struct dwmci_host *host = mmc->priv; |
Jaehoon Chung | 7cf7307 | 2012-10-15 19:10:29 +0000 | [diff] [blame] | 354 | |
Jaehoon Chung | 42f81a8 | 2013-11-29 20:08:57 +0900 | [diff] [blame] | 355 | if (host->board_init) |
| 356 | host->board_init(host); |
Rajeshwari Shinde | 7016309 | 2013-10-29 12:53:13 +0530 | [diff] [blame] | 357 | |
Jaehoon Chung | 7cf7307 | 2012-10-15 19:10:29 +0000 | [diff] [blame] | 358 | dwmci_writel(host, DWMCI_PWREN, 1); |
| 359 | |
| 360 | if (!dwmci_wait_reset(host, DWMCI_RESET_ALL)) { |
Simon Glass | 4c9b948 | 2015-08-06 20:16:27 -0600 | [diff] [blame] | 361 | debug("%s[%d] Fail-reset!!\n", __func__, __LINE__); |
| 362 | return -EIO; |
Jaehoon Chung | 7cf7307 | 2012-10-15 19:10:29 +0000 | [diff] [blame] | 363 | } |
| 364 | |
Amar | 902664c | 2013-04-27 11:42:54 +0530 | [diff] [blame] | 365 | /* Enumerate at 400KHz */ |
Pantelis Antoniou | 2c85046 | 2014-03-11 19:34:20 +0200 | [diff] [blame] | 366 | dwmci_setup_bus(host, mmc->cfg->f_min); |
Amar | 902664c | 2013-04-27 11:42:54 +0530 | [diff] [blame] | 367 | |
Jaehoon Chung | 7cf7307 | 2012-10-15 19:10:29 +0000 | [diff] [blame] | 368 | dwmci_writel(host, DWMCI_RINTSTS, 0xFFFFFFFF); |
| 369 | dwmci_writel(host, DWMCI_INTMASK, 0); |
| 370 | |
| 371 | dwmci_writel(host, DWMCI_TMOUT, 0xFFFFFFFF); |
| 372 | |
| 373 | dwmci_writel(host, DWMCI_IDINTEN, 0); |
| 374 | dwmci_writel(host, DWMCI_BMOD, 1); |
| 375 | |
Simon Glass | 6133efa | 2015-08-06 20:16:29 -0600 | [diff] [blame] | 376 | if (!host->fifoth_val) { |
| 377 | uint32_t fifo_size; |
| 378 | |
| 379 | fifo_size = dwmci_readl(host, DWMCI_FIFOTH); |
| 380 | fifo_size = ((fifo_size & RX_WMARK_MASK) >> RX_WMARK_SHIFT) + 1; |
| 381 | host->fifoth_val = MSIZE(0x2) | RX_WMARK(fifo_size / 2 - 1) | |
| 382 | TX_WMARK(fifo_size / 2); |
Amar | 902664c | 2013-04-27 11:42:54 +0530 | [diff] [blame] | 383 | } |
Simon Glass | 6133efa | 2015-08-06 20:16:29 -0600 | [diff] [blame] | 384 | dwmci_writel(host, DWMCI_FIFOTH, host->fifoth_val); |
Jaehoon Chung | 7cf7307 | 2012-10-15 19:10:29 +0000 | [diff] [blame] | 385 | |
| 386 | dwmci_writel(host, DWMCI_CLKENA, 0); |
| 387 | dwmci_writel(host, DWMCI_CLKSRC, 0); |
| 388 | |
| 389 | return 0; |
| 390 | } |
| 391 | |
Pantelis Antoniou | c9e7591 | 2014-02-26 19:28:45 +0200 | [diff] [blame] | 392 | static const struct mmc_ops dwmci_ops = { |
| 393 | .send_cmd = dwmci_send_cmd, |
| 394 | .set_ios = dwmci_set_ios, |
| 395 | .init = dwmci_init, |
| 396 | }; |
| 397 | |
Jaehoon Chung | 7cf7307 | 2012-10-15 19:10:29 +0000 | [diff] [blame] | 398 | int add_dwmci(struct dwmci_host *host, u32 max_clk, u32 min_clk) |
| 399 | { |
Pantelis Antoniou | 2c85046 | 2014-03-11 19:34:20 +0200 | [diff] [blame] | 400 | host->cfg.name = host->name; |
| 401 | host->cfg.ops = &dwmci_ops; |
| 402 | host->cfg.f_min = min_clk; |
| 403 | host->cfg.f_max = max_clk; |
Jaehoon Chung | 7cf7307 | 2012-10-15 19:10:29 +0000 | [diff] [blame] | 404 | |
Pantelis Antoniou | 2c85046 | 2014-03-11 19:34:20 +0200 | [diff] [blame] | 405 | host->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; |
Jaehoon Chung | 7cf7307 | 2012-10-15 19:10:29 +0000 | [diff] [blame] | 406 | |
Pantelis Antoniou | 2c85046 | 2014-03-11 19:34:20 +0200 | [diff] [blame] | 407 | host->cfg.host_caps = host->caps; |
Jaehoon Chung | 7cf7307 | 2012-10-15 19:10:29 +0000 | [diff] [blame] | 408 | |
| 409 | if (host->buswidth == 8) { |
Pantelis Antoniou | 2c85046 | 2014-03-11 19:34:20 +0200 | [diff] [blame] | 410 | host->cfg.host_caps |= MMC_MODE_8BIT; |
| 411 | host->cfg.host_caps &= ~MMC_MODE_4BIT; |
Jaehoon Chung | 7cf7307 | 2012-10-15 19:10:29 +0000 | [diff] [blame] | 412 | } else { |
Pantelis Antoniou | 2c85046 | 2014-03-11 19:34:20 +0200 | [diff] [blame] | 413 | host->cfg.host_caps |= MMC_MODE_4BIT; |
| 414 | host->cfg.host_caps &= ~MMC_MODE_8BIT; |
Jaehoon Chung | 7cf7307 | 2012-10-15 19:10:29 +0000 | [diff] [blame] | 415 | } |
Rob Herring | 5fd3edd | 2015-03-23 17:56:59 -0500 | [diff] [blame] | 416 | host->cfg.host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz; |
Pantelis Antoniou | 2c85046 | 2014-03-11 19:34:20 +0200 | [diff] [blame] | 417 | |
| 418 | host->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; |
Jaehoon Chung | 7cf7307 | 2012-10-15 19:10:29 +0000 | [diff] [blame] | 419 | |
Pantelis Antoniou | 2c85046 | 2014-03-11 19:34:20 +0200 | [diff] [blame] | 420 | host->mmc = mmc_create(&host->cfg, host); |
| 421 | if (host->mmc == NULL) |
| 422 | return -1; |
Jaehoon Chung | 7cf7307 | 2012-10-15 19:10:29 +0000 | [diff] [blame] | 423 | |
Pantelis Antoniou | 2c85046 | 2014-03-11 19:34:20 +0200 | [diff] [blame] | 424 | return 0; |
Jaehoon Chung | 7cf7307 | 2012-10-15 19:10:29 +0000 | [diff] [blame] | 425 | } |