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git01.mediatek.com / filogic / uboot / c893f21ee3b173f6e7b3c40bad7ec1f68d410012 / . / arch / m68k / cpu / mcf547x_8x / start.S
blob: fecf253d4bba4cf767c60038d915682ed28c1ed7 [file] [log] [blame]
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600[diff] [blame]1/*
2 * Copyright (C) 2003 Josef Baumgartner <josef.baumgartner@telex.de>
3 * Based on code from Bernhard Kuhn <bkuhn@metrowerks.com>
4 *
Wolfgang Denkbd8ec7e2013-10-07 13:07:26 +0200[diff] [blame]5 * SPDX-License-Identifier: GPL-2.0+
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600[diff] [blame]6 */
7
Wolfgang Denk0191e472010-10-26 14:34:52 +0200[diff] [blame]8#include <asm-offsets.h>
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600[diff] [blame]9#include <config.h>
10#include "version.h"
TsiChung Liew0ee47d42010-03-11 22:12:53 -0600[diff] [blame]11#include <asm/cache.h>
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600[diff] [blame]12
13#ifndef CONFIG_IDENT_STRING
14#define CONFIG_IDENT_STRING ""
15#endif
16
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600[diff] [blame]17#define _START _start
18#define _FAULT _fault
19
20#define SAVE_ALL \
21 move.w #0x2700,%sr; /* disable intrs */ \
22 subl #60,%sp; /* space for 15 regs */ \
23 moveml %d0-%d7/%a0-%a6,%sp@;
24
25#define RESTORE_ALL \
26 moveml %sp@,%d0-%d7/%a0-%a6; \
27 addl #60,%sp; /* space for 15 regs */ \
28 rte;
29
30.text
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]31
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600[diff] [blame]32/*
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]33 * Vector table. This is used for initial platform startup.
34 * These vectors are to catch any un-intended traps.
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600[diff] [blame]35 */
36_vectors:
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]37INITSP: .long 0x00000000 /* Initial SP */
38INITPC: .long _START /* Initial PC */
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600[diff] [blame]39
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]40vector02_0F:
41.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
42.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600[diff] [blame]43
44/* Reserved */
45vector10_17:
46.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
47
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]48vector18_1F:
49.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600[diff] [blame]50
51/* TRAP #0 - #15 */
52vector20_2F:
53.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
54.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
55
56/* Reserved */
57vector30_3F:
58.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
59.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
60
61vector64_127:
62.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
63.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
64.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
65.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
66.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
67.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
68.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
69.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
70
71vector128_191:
72.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
73.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
74.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
75.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
76.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
77.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
78.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
79.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
80
81vector192_255:
82.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
83.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
84.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
85.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
86.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
87.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
88.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
89.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
90
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]91.text
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600[diff] [blame]92
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]93.globl _start
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600[diff] [blame]94_start:
95 nop
96 nop
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]97 move.w #0x2700,%sr /* Mask off Interrupt */
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600[diff] [blame]98
99 /* Set vector base register at the beginning of the Flash */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]100 move.l #CONFIG_SYS_FLASH_BASE, %d0
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600[diff] [blame]101 movec %d0, %VBR
102
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]103 move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600[diff] [blame]104 movec %d0, %RAMBAR0
105
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]106 move.l #(CONFIG_SYS_INIT_RAM1_ADDR + CONFIG_SYS_INIT_RAM1_CTRL), %d0
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600[diff] [blame]107 movec %d0, %RAMBAR1
108
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]109 move.l #CONFIG_SYS_MBAR, %d0 /* set MBAR address */
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600[diff] [blame]110 move.c %d0, %MBAR
111
112 /* invalidate and disable cache */
113 move.l #0x01040100, %d0 /* Invalidate cache cmd */
114 movec %d0, %CACR /* Invalidate cache */
115 move.l #0, %d0
116 movec %d0, %ACR0
117 movec %d0, %ACR1
118 movec %d0, %ACR2
119 movec %d0, %ACR3
120
121 /* initialize general use internal ram */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]122 move.l #0, %d0
123 move.l #(ICACHE_STATUS), %a1 /* icache */
124 move.l #(DCACHE_STATUS), %a2 /* icache */
125 move.l %d0, (%a1)
126 move.l %d0, (%a2)
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600[diff] [blame]127
angelo@sysam.itef9707c2016-04-27 21:50:44 +0200[diff] [blame]128 /* put relocation table address to a5 */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]129 move.l #__got_start, %a5
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600[diff] [blame]130
angelo@sysam.itef9707c2016-04-27 21:50:44 +0200[diff] [blame]131 /* setup stack initially on top of internal static ram */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]132 move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE), %sp
angelo@sysam.itef9707c2016-04-27 21:50:44 +0200[diff] [blame]133
134 /*
135 * if configured, malloc_f arena will be reserved first,
136 * then (and always) gd struct space will be reserved
137 */
138 move.l %sp, -(%sp)
139 bsr board_init_f_alloc_reserve
140
141 /* update stack and frame-pointers */
142 move.l %d0, %sp
143 move.l %sp, %fp
144
145 /* initialize reserved area */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]146 move.l %d0, -(%sp)
147 bsr board_init_f_init_reserve
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600[diff] [blame]148
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]149 /* run low-level CPU init code (from flash) */
150 jbsr cpu_init_f
151
152 /* run low-level board init code (from flash) */
153 clr.l %sp@-
154 jbsr board_init_f
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600[diff] [blame]155
156 /* board_init_f() does not return */
157
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]158/******************************************************************************/
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600[diff] [blame]159
160/*
161 * void relocate_code (addr_sp, gd, addr_moni)
162 *
163 * This "function" does not return, instead it continues in RAM
164 * after relocating the monitor code.
165 *
166 * r3 = dest
167 * r4 = src
168 * r5 = length in bytes
169 * r6 = cachelinesize
170 */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]171.globl relocate_code
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600[diff] [blame]172relocate_code:
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]173 link.w %a6,#0
174 move.l 8(%a6), %sp /* set new stack pointer */
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600[diff] [blame]175
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]176 move.l 12(%a6), %d0 /* Save copy of Global Data pointer */
177 move.l 16(%a6), %a0 /* Save copy of Destination Address */
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600[diff] [blame]178
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]179 move.l #CONFIG_SYS_MONITOR_BASE, %a1
180 move.l #__init_end, %a2
181 move.l %a0, %a3
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600[diff] [blame]182
183 /* copy the code to RAM */
1841:
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]185 move.l (%a1)+, (%a3)+
186 cmp.l %a1,%a2
187 bgt.s 1b
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600[diff] [blame]188
189/*
190 * We are done. Do not return, instead branch to second part of board
191 * initialization, now running from RAM.
192 */
193 move.l %a0, %a1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]194 add.l #(in_ram - CONFIG_SYS_MONITOR_BASE), %a1
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600[diff] [blame]195 jmp (%a1)
196
197in_ram:
198
199clear_bss:
200 /*
201 * Now clear BSS segment
202 */
203 move.l %a0, %a1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]204 add.l #(_sbss - CONFIG_SYS_MONITOR_BASE),%a1
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600[diff] [blame]205 move.l %a0, %d1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]206 add.l #(_ebss - CONFIG_SYS_MONITOR_BASE),%d1
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600[diff] [blame]2076:
208 clr.l (%a1)+
209 cmp.l %a1,%d1
210 bgt.s 6b
211
212 /*
213 * fix got table in RAM
214 */
215 move.l %a0, %a1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]216 add.l #(__got_start - CONFIG_SYS_MONITOR_BASE),%a1
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]217 move.l %a1,%a5 /* fix got pointer register a5 */
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600[diff] [blame]218
219 move.l %a0, %a2
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]220 add.l #(__got_end - CONFIG_SYS_MONITOR_BASE),%a2
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600[diff] [blame]221
2227:
223 move.l (%a1),%d1
224 sub.l #_start,%d1
225 add.l %a0,%d1
226 move.l %d1,(%a1)+
227 cmp.l %a2, %a1
228 bne 7b
229
230 /* calculate relative jump to board_init_r in ram */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]231 move.l %a0, %a1
232 add.l #(board_init_r - CONFIG_SYS_MONITOR_BASE), %a1
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600[diff] [blame]233
234 /* set parameters for board_init_r */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]235 move.l %a0,-(%sp) /* dest_addr */
236 move.l %d0,-(%sp) /* gd */
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600[diff] [blame]237 jsr (%a1)
238
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]239/******************************************************************************/
240
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600[diff] [blame]241/* exception code */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]242.globl _fault
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600[diff] [blame]243_fault:
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]244 bra _fault
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600[diff] [blame]245
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]246.globl _exc_handler
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600[diff] [blame]247_exc_handler:
248 SAVE_ALL
249 movel %sp,%sp@-
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]250 bsr exc_handler
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600[diff] [blame]251 addql #4,%sp
252 RESTORE_ALL
253
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]254.globl _int_handler
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600[diff] [blame]255_int_handler:
256 SAVE_ALL
257 movel %sp,%sp@-
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]258 bsr int_handler
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600[diff] [blame]259 addql #4,%sp
260 RESTORE_ALL
261
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]262/******************************************************************************/
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600[diff] [blame]263
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]264.globl version_string
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600[diff] [blame]265version_string:
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]266.ascii U_BOOT_VERSION_STRING, "\0"
267.align 4