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git01.mediatek.com / filogic / uboot / c88e90a74d92dff19e22ed4dac05bc4f85fb37f3 / . / dts / upstream / src / arm64 / intel / keembay-soc.dtsi
blob: ae00e9e54e82cbb99ad79c126a76ac51534443c1 [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
2/*
3 * Copyright (C) 2020, Intel Corporation.
4 *
5 * Device tree describing Keem Bay SoC.
6 */
7
8#include <dt-bindings/interrupt-controller/arm-gic.h>
9
10/ {
11 interrupt-parent = <&gic>;
12 #address-cells = <2>;
13 #size-cells = <2>;
14
15 cpus {
16 #address-cells = <1>;
17 #size-cells = <0>;
18
19 cpu@0 {
20 compatible = "arm,cortex-a53";
21 device_type = "cpu";
22 reg = <0x0>;
23 enable-method = "psci";
24 };
25
26 cpu@1 {
27 compatible = "arm,cortex-a53";
28 device_type = "cpu";
29 reg = <0x1>;
30 enable-method = "psci";
31 };
32
33 cpu@2 {
34 compatible = "arm,cortex-a53";
35 device_type = "cpu";
36 reg = <0x2>;
37 enable-method = "psci";
38 };
39
40 cpu@3 {
41 compatible = "arm,cortex-a53";
42 device_type = "cpu";
43 reg = <0x3>;
44 enable-method = "psci";
45 };
46 };
47
48 psci {
49 compatible = "arm,psci-0.2";
50 method = "smc";
51 };
52
53 gic: interrupt-controller@20500000 {
54 compatible = "arm,gic-v3";
55 interrupt-controller;
56 #interrupt-cells = <3>;
57 reg = <0x0 0x20500000 0x0 0x20000>, /* GICD */
58 <0x0 0x20580000 0x0 0x80000>; /* GICR */
59 /* VGIC maintenance interrupt */
60 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
61 };
62
63 timer {
64 compatible = "arm,armv8-timer";
65 /* Secure, non-secure, virtual, and hypervisor */
66 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
67 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
68 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
69 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
70 };
71
72 pmu {
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]73 compatible = "arm,cortex-a53-pmu";
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]74 interrupts = <GIC_PPI 0x7 IRQ_TYPE_LEVEL_HIGH>;
75 };
76
77 soc {
78 compatible = "simple-bus";
79 #address-cells = <2>;
80 #size-cells = <2>;
81 ranges;
82
83 uart0: serial@20150000 {
84 compatible = "snps,dw-apb-uart";
85 reg = <0x0 0x20150000 0x0 0x100>;
86 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
87 clock-frequency = <24000000>;
88 reg-shift = <2>;
89 reg-io-width = <4>;
90 status = "disabled";
91 };
92
93 uart1: serial@20160000 {
94 compatible = "snps,dw-apb-uart";
95 reg = <0x0 0x20160000 0x0 0x100>;
96 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
97 clock-frequency = <24000000>;
98 reg-shift = <2>;
99 reg-io-width = <4>;
100 status = "disabled";
101 };
102
103 uart2: serial@20170000 {
104 compatible = "snps,dw-apb-uart";
105 reg = <0x0 0x20170000 0x0 0x100>;
106 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
107 clock-frequency = <24000000>;
108 reg-shift = <2>;
109 reg-io-width = <4>;
110 status = "disabled";
111 };
112
113 uart3: serial@20180000 {
114 compatible = "snps,dw-apb-uart";
115 reg = <0x0 0x20180000 0x0 0x100>;
116 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
117 clock-frequency = <24000000>;
118 reg-shift = <2>;
119 reg-io-width = <4>;
120 status = "disabled";
121 };
122 };
123};