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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
wdenkc4cbd342005-01-09 18:21:42 +00002/*
3 * Configuation settings for the Sentec Cobra Board.
4 *
5 * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
wdenkc4cbd342005-01-09 18:21:42 +00006 */
7
8/* ---
Bin Meng75574052016-02-05 19:30:11 -08009 * Version: U-Boot 1.0.0 - initial release for Sentec COBRA5272 board
wdenkc4cbd342005-01-09 18:21:42 +000010 * Date: 2004-03-29
11 * Author: Florian Schlote
12 *
13 * For a description of configuration options please refer also to the
14 * general u-boot-1.x.x/README file
15 * ---
16 */
17
18/* ---
19 * board/config.h - configuration options, board specific
20 * ---
21 */
22
23#ifndef _CONFIG_COBRA5272_H
24#define _CONFIG_COBRA5272_H
25
26/* ---
wdenkc4cbd342005-01-09 18:21:42 +000027 * Defines processor clock - important for correct timings concerning serial
28 * interface etc.
wdenkc4cbd342005-01-09 18:21:42 +000029 * ---
30 */
31
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020032#define CONFIG_SYS_CLK 66000000
33#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
wdenkc4cbd342005-01-09 18:21:42 +000034
TsiChungLiewcfa2b482007-08-15 19:41:06 -050035/* Enable Dma Timer */
36#define CONFIG_MCFTMR
wdenkc4cbd342005-01-09 18:21:42 +000037
38/* ---
39 * Define baudrate for UART1 (console output, tftp, ...)
40 * default value of CONFIG_BAUDRATE for Sentec board: 19200 baud
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020041 * CONFIG_SYS_BAUDRATE_TABLE defines values that can be selected in u-boot command
wdenkc4cbd342005-01-09 18:21:42 +000042 * interface
43 * ---
44 */
45
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020046#define CONFIG_SYS_UART_PORT (0)
wdenkc4cbd342005-01-09 18:21:42 +000047
48/* ---
49 * set "#if 0" to "#if 1" if (Hardware)-WATCHDOG should be enabled & change
50 * timeout acc. to your needs
51 * #define CONFIG_WATCHDOG_TIMEOUT x , x is timeout in milliseconds, e. g. 10000
52 * for 10 sec
53 * ---
54 */
55
56#if 0
57#define CONFIG_WATCHDOG
58#define CONFIG_WATCHDOG_TIMEOUT 10000 /* timeout in milliseconds */
59#endif
60
61/* ---
62 * CONFIG_MONITOR_IS_IN_RAM defines if u-boot is started from a different
63 * bootloader residing in flash ('chainloading'); if you want to use
64 * chainloading or want to compile a u-boot binary that can be loaded into
65 * RAM via BDM set
Wolfgang Denka1be4762008-05-20 16:00:29 +020066 * "#if 0" to "#if 1"
wdenkc4cbd342005-01-09 18:21:42 +000067 * You will need a first stage bootloader then, e. g. colilo or a working BDM
68 * cable (Background Debug Mode)
69 *
70 * Setting #if 0: u-boot will start from flash and relocate itself to RAM
71 *
Wolfgang Denk0708bc62010-10-07 21:51:12 +020072 * Please do not forget to modify the setting of CONFIG_SYS_TEXT_BASE
wdenkc4cbd342005-01-09 18:21:42 +000073 * in board/cobra5272/config.mk accordingly (#if 0: 0xffe00000; #if 1: 0x20000)
74 *
75 * ---
76 */
77
78#if 0
79#define CONFIG_MONITOR_IS_IN_RAM /* monitor is started from a preloader */
80#endif
81
82/* ---
83 * Configuration for environment
84 * Environment is embedded in u-boot in the second sector of the flash
85 * ---
86 */
87
angelo@sysam.it6312a952015-03-29 22:54:16 +020088#define LDS_BOARD_TEXT \
Simon Glass547cb402017-08-03 12:21:49 -060089 . = DEFINED(env_offset) ? env_offset : .; \
90 env/embedded.o(.text);
Jon Loeliger37ec35e2007-07-04 22:31:56 -050091
92/*
Jon Loeligere54e77a2007-07-10 09:29:01 -050093 * BOOTP options
94 */
95#define CONFIG_BOOTP_BOOTFILESIZE
Jon Loeligere54e77a2007-07-10 09:29:01 -050096
TsiChungLiewcfa2b482007-08-15 19:41:06 -050097#ifdef CONFIG_MCFFEC
TsiChung Liewb3162452008-03-30 01:22:13 -050098# define CONFIG_MII_INIT 1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020099# define CONFIG_SYS_DISCOVER_PHY
100# define CONFIG_SYS_RX_ETH_BUFFER 8
101# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200102/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
103# ifndef CONFIG_SYS_DISCOVER_PHY
TsiChungLiewcfa2b482007-08-15 19:41:06 -0500104# define FECDUPLEX FULL
105# define FECSPEED _100BASET
106# else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200107# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
108# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
TsiChungLiewcfa2b482007-08-15 19:41:06 -0500109# endif
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200110# endif /* CONFIG_SYS_DISCOVER_PHY */
TsiChungLiewcfa2b482007-08-15 19:41:06 -0500111#endif
wdenkc4cbd342005-01-09 18:21:42 +0000112
113/*
114 *-----------------------------------------------------------------------------
115 * Define user parameters that have to be customized most likely
116 *-----------------------------------------------------------------------------
117 */
118
119/*AUTOBOOT settings - booting images automatically by u-boot after power on*/
120
wdenkc4cbd342005-01-09 18:21:42 +0000121/* The following settings will be contained in the environment block ; if you
122want to use a neutral environment all those settings can be manually set in
123u-boot: 'set' command */
124
125#if 0
126
wdenkc4cbd342005-01-09 18:21:42 +0000127enter a valid image address in flash */
128
wdenkc4cbd342005-01-09 18:21:42 +0000129/* User network settings */
130
wdenkc4cbd342005-01-09 18:21:42 +0000131#define CONFIG_IPADDR 192.168.100.2 /* default board IP address */
132#define CONFIG_SERVERIP 192.168.100.1 /* default tftp server IP address */
133
134#endif
135
wdenkc4cbd342005-01-09 18:21:42 +0000136/*---*/
137
wdenkc4cbd342005-01-09 18:21:42 +0000138/*
139 *-----------------------------------------------------------------------------
140 * End of user parameters to be customized
141 *-----------------------------------------------------------------------------
142 */
143
144/* ---
145 * Defines memory range for test
146 * ---
147 */
148
wdenkc4cbd342005-01-09 18:21:42 +0000149/* ---
150 * Low Level Configuration Settings
151 * (address mappings, register initial values, etc.)
152 * You should know what you are doing if you make changes here.
153 * ---
154 */
155
156/* ---
157 * Base register address
158 * ---
159 */
160
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200161#define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */
wdenkc4cbd342005-01-09 18:21:42 +0000162
163/* ---
164 * System Conf. Reg. & System Protection Reg.
165 * ---
166 */
167
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200168#define CONFIG_SYS_SCR 0x0003
169#define CONFIG_SYS_SPR 0xffff
wdenkc4cbd342005-01-09 18:21:42 +0000170
171/* ---
172 * Ethernet settings
173 * ---
174 */
175
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200176#define CONFIG_SYS_DISCOVER_PHY
177#define CONFIG_SYS_ENET_BD_BASE 0x780000
wdenkc4cbd342005-01-09 18:21:42 +0000178
179/*-----------------------------------------------------------------------
180 * Definitions for initial stack pointer and data area (in internal SRAM)
181 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200182#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
Wolfgang Denk1c2e98e2010-10-26 13:32:32 +0200183#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */
Wolfgang Denk0191e472010-10-26 14:34:52 +0200184#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200185#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenkc4cbd342005-01-09 18:21:42 +0000186
187/*-----------------------------------------------------------------------
188 * Start addresses for the final memory configuration
189 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200190 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenkc4cbd342005-01-09 18:21:42 +0000191 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200192#define CONFIG_SYS_SDRAM_BASE 0x00000000
wdenkc4cbd342005-01-09 18:21:42 +0000193
194/*
195 *-------------------------------------------------------------------------
196 * RAM SIZE (is defined above)
197 *-----------------------------------------------------------------------
198 */
199
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200200/* #define CONFIG_SYS_SDRAM_SIZE 16 */
wdenkc4cbd342005-01-09 18:21:42 +0000201
202/*
203 *-----------------------------------------------------------------------
204 */
205
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200206#define CONFIG_SYS_FLASH_BASE 0xffe00000
wdenkc4cbd342005-01-09 18:21:42 +0000207
208#ifdef CONFIG_MONITOR_IS_IN_RAM
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200209#define CONFIG_SYS_MONITOR_BASE 0x20000
wdenkc4cbd342005-01-09 18:21:42 +0000210#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200211#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
wdenkc4cbd342005-01-09 18:21:42 +0000212#endif
213
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200214#define CONFIG_SYS_MONITOR_LEN 0x20000
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200215#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
wdenkc4cbd342005-01-09 18:21:42 +0000216
217/*
218 * For booting Linux, the board info and command line data
219 * have to be in the first 8 MB of memory, since this is
220 * the maximum mapped by the Linux kernel during initialization ??
221 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200222#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenkc4cbd342005-01-09 18:21:42 +0000223
224/*-----------------------------------------------------------------------
225 * FLASH organization
226 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200227#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
228#define CONFIG_SYS_MAX_FLASH_SECT 11 /* max number of sectors on one chip */
229#define CONFIG_SYS_FLASH_ERASE_TOUT 1000 /* flash timeout */
wdenkc4cbd342005-01-09 18:21:42 +0000230
231/*-----------------------------------------------------------------------
232 * Cache Configuration
233 */
wdenkc4cbd342005-01-09 18:21:42 +0000234
TsiChung Liew0ee47d42010-03-11 22:12:53 -0600235#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
Wolfgang Denk1c2e98e2010-10-26 13:32:32 +0200236 CONFIG_SYS_INIT_RAM_SIZE - 8)
TsiChung Liew0ee47d42010-03-11 22:12:53 -0600237#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
Wolfgang Denk1c2e98e2010-10-26 13:32:32 +0200238 CONFIG_SYS_INIT_RAM_SIZE - 4)
TsiChung Liew0ee47d42010-03-11 22:12:53 -0600239#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI)
240#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
241 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
242 CF_ACR_EN | CF_ACR_SM_ALL)
243#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \
244 CF_CACR_DISD | CF_CACR_INVI | \
245 CF_CACR_CEIB | CF_CACR_DCM | \
246 CF_CACR_EUSP)
247
wdenkc4cbd342005-01-09 18:21:42 +0000248/*-----------------------------------------------------------------------
wdenkc4cbd342005-01-09 18:21:42 +0000249 * LED config
250 */
251#define LED_STAT_0 0xffff /*all LEDs off*/
252#define LED_STAT_1 0xfffe
253#define LED_STAT_2 0xfffd
254#define LED_STAT_3 0xfffb
255#define LED_STAT_4 0xfff7
256#define LED_STAT_5 0xffef
257#define LED_STAT_6 0xffdf
258#define LED_STAT_7 0xff00 /*all LEDs on*/
259
260/*-----------------------------------------------------------------------
261 * Port configuration (GPIO)
262 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200263#define CONFIG_SYS_PACNT 0x00000000 /* PortA control reg.: All pins are external
wdenkc4cbd342005-01-09 18:21:42 +0000264GPIO*/
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200265#define CONFIG_SYS_PADDR 0x00FF /* PortA direction reg.: PA7 to PA0 are outputs
wdenkc4cbd342005-01-09 18:21:42 +0000266(1^=output, 0^=input) */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200267#define CONFIG_SYS_PADAT LED_STAT_0 /* PortA value reg.: Turn all LED off */
268#define CONFIG_SYS_PBCNT 0x55554155 /* PortB control reg.: Ethernet/UART
wdenkc4cbd342005-01-09 18:21:42 +0000269configuration */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200270#define CONFIG_SYS_PBDDR 0x0000 /* PortB direction: All pins configured as inputs */
271#define CONFIG_SYS_PBDAT 0x0000 /* PortB value reg. */
272#define CONFIG_SYS_PDCNT 0x00000000 /* PortD control reg. */
wdenkc4cbd342005-01-09 18:21:42 +0000273
274#endif /* _CONFIG_COBRA5272_H */