Stefan Roese | 42fbddd | 2006-09-07 11:51:23 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Overview: |
| 3 | * Platform independend driver for NDFC (NanD Flash Controller) |
Stefan Roese | 982511e | 2009-05-20 10:58:01 +0200 | [diff] [blame] | 4 | * integrated into IBM/AMCC PPC4xx cores |
Stefan Roese | 42fbddd | 2006-09-07 11:51:23 +0200 | [diff] [blame] | 5 | * |
Stefan Roese | 982511e | 2009-05-20 10:58:01 +0200 | [diff] [blame] | 6 | * (C) Copyright 2006-2009 |
Stefan Roese | 42fbddd | 2006-09-07 11:51:23 +0200 | [diff] [blame] | 7 | * Stefan Roese, DENX Software Engineering, sr@denx.de. |
| 8 | * |
| 9 | * Based on original work by |
| 10 | * Thomas Gleixner |
| 11 | * Copyright 2006 IBM |
| 12 | * |
| 13 | * See file CREDITS for list of people who contributed to this |
| 14 | * project. |
| 15 | * |
| 16 | * This program is free software; you can redistribute it and/or |
| 17 | * modify it under the terms of the GNU General Public License as |
| 18 | * published by the Free Software Foundation; either version 2 of |
| 19 | * the License, or (at your option) any later version. |
| 20 | * |
| 21 | * This program is distributed in the hope that it will be useful, |
| 22 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 23 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 24 | * GNU General Public License for more details. |
| 25 | * |
| 26 | * You should have received a copy of the GNU General Public License |
| 27 | * along with this program; if not, write to the Free Software |
| 28 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 29 | * MA 02111-1307 USA |
| 30 | */ |
| 31 | |
| 32 | #include <common.h> |
Stefan Roese | 42fbddd | 2006-09-07 11:51:23 +0200 | [diff] [blame] | 33 | #include <nand.h> |
| 34 | #include <linux/mtd/ndfc.h> |
Stefan Roese | 1eb122a | 2007-06-01 15:15:12 +0200 | [diff] [blame] | 35 | #include <linux/mtd/nand_ecc.h> |
Stefan Roese | 42fbddd | 2006-09-07 11:51:23 +0200 | [diff] [blame] | 36 | #include <asm/processor.h> |
Stefan Roese | 1eb122a | 2007-06-01 15:15:12 +0200 | [diff] [blame] | 37 | #include <asm/io.h> |
Stefan Roese | 247e9d7 | 2010-09-09 19:18:00 +0200 | [diff] [blame] | 38 | #include <asm/ppc4xx.h> |
Stefan Roese | 42fbddd | 2006-09-07 11:51:23 +0200 | [diff] [blame] | 39 | |
Alex Waterman | cd6aae3 | 2011-05-19 15:08:36 -0400 | [diff] [blame] | 40 | #ifndef CONFIG_SYS_NAND_BCR |
| 41 | #define CONFIG_SYS_NAND_BCR 0x80002222 |
| 42 | #endif |
| 43 | #ifndef CONFIG_SYS_NDFC_EBC0_CFG |
| 44 | #define CONFIG_SYS_NDFC_EBC0_CFG 0xb8400000 |
| 45 | #endif |
| 46 | |
Stefan Roese | 0556a2a | 2008-01-05 16:47:58 +0100 | [diff] [blame] | 47 | /* |
| 48 | * We need to store the info, which chip-select (CS) is used for the |
| 49 | * chip number. For example on Sequoia NAND chip #0 uses |
| 50 | * CS #3. |
| 51 | */ |
| 52 | static int ndfc_cs[NDFC_MAX_BANKS]; |
Stefan Roese | 42fbddd | 2006-09-07 11:51:23 +0200 | [diff] [blame] | 53 | |
William Juul | 52c0796 | 2007-10-31 13:53:06 +0100 | [diff] [blame] | 54 | static void ndfc_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) |
Stefan Roese | 42fbddd | 2006-09-07 11:51:23 +0200 | [diff] [blame] | 55 | { |
William Juul | 9e9c2c1 | 2007-11-09 13:32:30 +0100 | [diff] [blame] | 56 | struct nand_chip *this = mtd->priv; |
Stefan Roese | 0556a2a | 2008-01-05 16:47:58 +0100 | [diff] [blame] | 57 | ulong base = (ulong) this->IO_ADDR_W & 0xffffff00; |
Stefan Roese | 42fbddd | 2006-09-07 11:51:23 +0200 | [diff] [blame] | 58 | |
Stefan Roese | 0556a2a | 2008-01-05 16:47:58 +0100 | [diff] [blame] | 59 | if (cmd == NAND_CMD_NONE) |
| 60 | return; |
Stefan Roese | 42fbddd | 2006-09-07 11:51:23 +0200 | [diff] [blame] | 61 | |
Stefan Roese | 0556a2a | 2008-01-05 16:47:58 +0100 | [diff] [blame] | 62 | if (ctrl & NAND_CLE) |
| 63 | out_8((u8 *)(base + NDFC_CMD), cmd & 0xFF); |
| 64 | else |
| 65 | out_8((u8 *)(base + NDFC_ALE), cmd & 0xFF); |
Stefan Roese | 42fbddd | 2006-09-07 11:51:23 +0200 | [diff] [blame] | 66 | } |
| 67 | |
| 68 | static int ndfc_dev_ready(struct mtd_info *mtdinfo) |
| 69 | { |
Wolfgang Denk | 4df0da5 | 2006-10-09 00:42:01 +0200 | [diff] [blame] | 70 | struct nand_chip *this = mtdinfo->priv; |
Stefan Roese | 0556a2a | 2008-01-05 16:47:58 +0100 | [diff] [blame] | 71 | ulong base = (ulong) this->IO_ADDR_W & 0xffffff00; |
Stefan Roese | 42fbddd | 2006-09-07 11:51:23 +0200 | [diff] [blame] | 72 | |
Stefan Roese | 0556a2a | 2008-01-05 16:47:58 +0100 | [diff] [blame] | 73 | return (in_be32((u32 *)(base + NDFC_STAT)) & NDFC_STAT_IS_READY); |
Stefan Roese | 42fbddd | 2006-09-07 11:51:23 +0200 | [diff] [blame] | 74 | } |
| 75 | |
Stefan Roese | 1eb122a | 2007-06-01 15:15:12 +0200 | [diff] [blame] | 76 | static void ndfc_enable_hwecc(struct mtd_info *mtdinfo, int mode) |
| 77 | { |
| 78 | struct nand_chip *this = mtdinfo->priv; |
Stefan Roese | 0556a2a | 2008-01-05 16:47:58 +0100 | [diff] [blame] | 79 | ulong base = (ulong) this->IO_ADDR_W & 0xffffff00; |
Stefan Roese | 1eb122a | 2007-06-01 15:15:12 +0200 | [diff] [blame] | 80 | u32 ccr; |
| 81 | |
| 82 | ccr = in_be32((u32 *)(base + NDFC_CCR)); |
| 83 | ccr |= NDFC_CCR_RESET_ECC; |
| 84 | out_be32((u32 *)(base + NDFC_CCR), ccr); |
| 85 | } |
| 86 | |
| 87 | static int ndfc_calculate_ecc(struct mtd_info *mtdinfo, |
| 88 | const u_char *dat, u_char *ecc_code) |
| 89 | { |
| 90 | struct nand_chip *this = mtdinfo->priv; |
Stefan Roese | 0556a2a | 2008-01-05 16:47:58 +0100 | [diff] [blame] | 91 | ulong base = (ulong) this->IO_ADDR_W & 0xffffff00; |
Stefan Roese | 1eb122a | 2007-06-01 15:15:12 +0200 | [diff] [blame] | 92 | u32 ecc; |
| 93 | u8 *p = (u8 *)&ecc; |
| 94 | |
| 95 | ecc = in_be32((u32 *)(base + NDFC_ECC)); |
| 96 | |
| 97 | /* The NDFC uses Smart Media (SMC) bytes order |
| 98 | */ |
Feng Kan | 50db6f2 | 2009-08-21 10:59:42 -0700 | [diff] [blame] | 99 | ecc_code[0] = p[1]; |
| 100 | ecc_code[1] = p[2]; |
Stefan Roese | 1eb122a | 2007-06-01 15:15:12 +0200 | [diff] [blame] | 101 | ecc_code[2] = p[3]; |
| 102 | |
| 103 | return 0; |
| 104 | } |
Stefan Roese | 42fbddd | 2006-09-07 11:51:23 +0200 | [diff] [blame] | 105 | |
| 106 | /* |
| 107 | * Speedups for buffer read/write/verify |
| 108 | * |
| 109 | * NDFC allows 32bit read/write of data. So we can speed up the buffer |
| 110 | * functions. No further checking, as nand_base will always read/write |
| 111 | * page aligned. |
| 112 | */ |
| 113 | static void ndfc_read_buf(struct mtd_info *mtdinfo, uint8_t *buf, int len) |
| 114 | { |
Wolfgang Denk | 4df0da5 | 2006-10-09 00:42:01 +0200 | [diff] [blame] | 115 | struct nand_chip *this = mtdinfo->priv; |
Stefan Roese | 0556a2a | 2008-01-05 16:47:58 +0100 | [diff] [blame] | 116 | ulong base = (ulong) this->IO_ADDR_W & 0xffffff00; |
Stefan Roese | 42fbddd | 2006-09-07 11:51:23 +0200 | [diff] [blame] | 117 | uint32_t *p = (uint32_t *) buf; |
| 118 | |
Stefan Roese | 3cdd3fd | 2006-10-20 14:28:52 +0200 | [diff] [blame] | 119 | for (;len > 0; len -= 4) |
Stefan Roese | 1eb122a | 2007-06-01 15:15:12 +0200 | [diff] [blame] | 120 | *p++ = in_be32((u32 *)(base + NDFC_DATA)); |
Stefan Roese | 42fbddd | 2006-09-07 11:51:23 +0200 | [diff] [blame] | 121 | } |
| 122 | |
Stefan Roese | 1eb122a | 2007-06-01 15:15:12 +0200 | [diff] [blame] | 123 | #ifndef CONFIG_NAND_SPL |
| 124 | /* |
| 125 | * Don't use these speedup functions in NAND boot image, since the image |
| 126 | * has to fit into 4kByte. |
| 127 | */ |
Stefan Roese | 42fbddd | 2006-09-07 11:51:23 +0200 | [diff] [blame] | 128 | static void ndfc_write_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len) |
| 129 | { |
Wolfgang Denk | 4df0da5 | 2006-10-09 00:42:01 +0200 | [diff] [blame] | 130 | struct nand_chip *this = mtdinfo->priv; |
Stefan Roese | 0556a2a | 2008-01-05 16:47:58 +0100 | [diff] [blame] | 131 | ulong base = (ulong) this->IO_ADDR_W & 0xffffff00; |
Stefan Roese | 42fbddd | 2006-09-07 11:51:23 +0200 | [diff] [blame] | 132 | uint32_t *p = (uint32_t *) buf; |
| 133 | |
Stefan Roese | 3cdd3fd | 2006-10-20 14:28:52 +0200 | [diff] [blame] | 134 | for (; len > 0; len -= 4) |
Stefan Roese | 1eb122a | 2007-06-01 15:15:12 +0200 | [diff] [blame] | 135 | out_be32((u32 *)(base + NDFC_DATA), *p++); |
Stefan Roese | 42fbddd | 2006-09-07 11:51:23 +0200 | [diff] [blame] | 136 | } |
| 137 | |
| 138 | static int ndfc_verify_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len) |
| 139 | { |
Wolfgang Denk | 4df0da5 | 2006-10-09 00:42:01 +0200 | [diff] [blame] | 140 | struct nand_chip *this = mtdinfo->priv; |
Stefan Roese | 0556a2a | 2008-01-05 16:47:58 +0100 | [diff] [blame] | 141 | ulong base = (ulong) this->IO_ADDR_W & 0xffffff00; |
Stefan Roese | 42fbddd | 2006-09-07 11:51:23 +0200 | [diff] [blame] | 142 | uint32_t *p = (uint32_t *) buf; |
| 143 | |
Stefan Roese | 3cdd3fd | 2006-10-20 14:28:52 +0200 | [diff] [blame] | 144 | for (; len > 0; len -= 4) |
Stefan Roese | 1eb122a | 2007-06-01 15:15:12 +0200 | [diff] [blame] | 145 | if (*p++ != in_be32((u32 *)(base + NDFC_DATA))) |
Stefan Roese | 42fbddd | 2006-09-07 11:51:23 +0200 | [diff] [blame] | 146 | return -1; |
| 147 | |
| 148 | return 0; |
| 149 | } |
Stefan Roese | 42fbddd | 2006-09-07 11:51:23 +0200 | [diff] [blame] | 150 | |
Alex Waterman | cd6aae3 | 2011-05-19 15:08:36 -0400 | [diff] [blame] | 151 | /* |
| 152 | * Read a byte from the NDFC. |
| 153 | */ |
| 154 | static uint8_t ndfc_read_byte(struct mtd_info *mtd) |
| 155 | { |
| 156 | |
| 157 | struct nand_chip *chip = mtd->priv; |
| 158 | |
| 159 | #ifdef CONFIG_SYS_NDFC_16BIT |
| 160 | return (uint8_t) readw(chip->IO_ADDR_R); |
| 161 | #else |
| 162 | return readb(chip->IO_ADDR_R); |
Wolfgang Ocker | aa36c3c | 2008-08-26 19:55:23 +0200 | [diff] [blame] | 163 | #endif |
| 164 | |
Alex Waterman | cd6aae3 | 2011-05-19 15:08:36 -0400 | [diff] [blame] | 165 | } |
| 166 | |
| 167 | #endif /* #ifndef CONFIG_NAND_SPL */ |
| 168 | |
Stefan Roese | 3cdd3fd | 2006-10-20 14:28:52 +0200 | [diff] [blame] | 169 | void board_nand_select_device(struct nand_chip *nand, int chip) |
| 170 | { |
Stefan Roese | d07e572 | 2006-10-24 18:06:48 +0200 | [diff] [blame] | 171 | /* |
| 172 | * Don't use "chip" to address the NAND device, |
| 173 | * generate the cs from the address where it is encoded. |
| 174 | */ |
Stefan Roese | 0556a2a | 2008-01-05 16:47:58 +0100 | [diff] [blame] | 175 | ulong base = (ulong)nand->IO_ADDR_W & 0xffffff00; |
| 176 | int cs = ndfc_cs[chip]; |
Stefan Roese | 3cdd3fd | 2006-10-20 14:28:52 +0200 | [diff] [blame] | 177 | |
| 178 | /* Set NandFlash Core Configuration Register */ |
Stefan Roese | 1eb122a | 2007-06-01 15:15:12 +0200 | [diff] [blame] | 179 | /* 1 col x 2 rows */ |
| 180 | out_be32((u32 *)(base + NDFC_CCR), 0x00000000 | (cs << 24)); |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 181 | out_be32((u32 *)(base + NDFC_BCFG0 + (cs << 2)), CONFIG_SYS_NAND_BCR); |
Stefan Roese | 3cdd3fd | 2006-10-20 14:28:52 +0200 | [diff] [blame] | 182 | } |
| 183 | |
Stefan Roese | 7b86c2b | 2008-08-29 11:56:49 +0200 | [diff] [blame] | 184 | static void ndfc_select_chip(struct mtd_info *mtd, int chip) |
| 185 | { |
| 186 | /* |
| 187 | * Nothing to do here! |
| 188 | */ |
| 189 | } |
| 190 | |
Heiko Schocher | 3ec4366 | 2006-12-21 17:17:02 +0100 | [diff] [blame] | 191 | int board_nand_init(struct nand_chip *nand) |
Stefan Roese | 42fbddd | 2006-09-07 11:51:23 +0200 | [diff] [blame] | 192 | { |
Stefan Roese | d07e572 | 2006-10-24 18:06:48 +0200 | [diff] [blame] | 193 | int cs = (ulong)nand->IO_ADDR_W & 0x00000003; |
Stefan Roese | 0556a2a | 2008-01-05 16:47:58 +0100 | [diff] [blame] | 194 | ulong base = (ulong)nand->IO_ADDR_W & 0xffffff00; |
| 195 | static int chip = 0; |
Stefan Roese | 3cdd3fd | 2006-10-20 14:28:52 +0200 | [diff] [blame] | 196 | |
Stefan Roese | 0556a2a | 2008-01-05 16:47:58 +0100 | [diff] [blame] | 197 | /* |
| 198 | * Save chip-select for this chip # |
| 199 | */ |
| 200 | ndfc_cs[chip] = cs; |
| 201 | |
| 202 | /* |
| 203 | * Select required NAND chip in NDFC |
| 204 | */ |
| 205 | board_nand_select_device(nand, chip); |
Stefan Roese | 42fbddd | 2006-09-07 11:51:23 +0200 | [diff] [blame] | 206 | |
Stefan Roese | 0556a2a | 2008-01-05 16:47:58 +0100 | [diff] [blame] | 207 | nand->IO_ADDR_R = (void __iomem *)(base + NDFC_DATA); |
| 208 | nand->IO_ADDR_W = (void __iomem *)(base + NDFC_DATA); |
| 209 | nand->cmd_ctrl = ndfc_hwcontrol; |
| 210 | nand->chip_delay = 50; |
| 211 | nand->read_buf = ndfc_read_buf; |
| 212 | nand->dev_ready = ndfc_dev_ready; |
William Juul | 9e9c2c1 | 2007-11-09 13:32:30 +0100 | [diff] [blame] | 213 | nand->ecc.correct = nand_correct_data; |
| 214 | nand->ecc.hwctl = ndfc_enable_hwecc; |
| 215 | nand->ecc.calculate = ndfc_calculate_ecc; |
| 216 | nand->ecc.mode = NAND_ECC_HW; |
| 217 | nand->ecc.size = 256; |
| 218 | nand->ecc.bytes = 3; |
Stefan Roese | 7b86c2b | 2008-08-29 11:56:49 +0200 | [diff] [blame] | 219 | nand->select_chip = ndfc_select_chip; |
Stefan Roese | 1eb122a | 2007-06-01 15:15:12 +0200 | [diff] [blame] | 220 | |
Alex Waterman | cd6aae3 | 2011-05-19 15:08:36 -0400 | [diff] [blame] | 221 | #ifdef CONFIG_SYS_NDFC_16BIT |
| 222 | nand->options |= NAND_BUSWIDTH_16; |
| 223 | #endif |
| 224 | |
Stefan Roese | 42fbddd | 2006-09-07 11:51:23 +0200 | [diff] [blame] | 225 | #ifndef CONFIG_NAND_SPL |
| 226 | nand->write_buf = ndfc_write_buf; |
Stefan Roese | 42fbddd | 2006-09-07 11:51:23 +0200 | [diff] [blame] | 227 | nand->verify_buf = ndfc_verify_buf; |
Alex Waterman | cd6aae3 | 2011-05-19 15:08:36 -0400 | [diff] [blame] | 228 | nand->read_byte = ndfc_read_byte; |
Stefan Roese | 585b5f54 | 2010-11-23 14:32:48 +0100 | [diff] [blame] | 229 | |
| 230 | chip++; |
Stefan Roese | 42fbddd | 2006-09-07 11:51:23 +0200 | [diff] [blame] | 231 | #else |
| 232 | /* |
| 233 | * Setup EBC (CS0 only right now) |
| 234 | */ |
Alex Waterman | cd6aae3 | 2011-05-19 15:08:36 -0400 | [diff] [blame] | 235 | mtebc(EBC0_CFG, CONFIG_SYS_NDFC_EBC0_CFG); |
Stefan Roese | 42fbddd | 2006-09-07 11:51:23 +0200 | [diff] [blame] | 236 | |
Stefan Roese | 918010a | 2009-09-09 16:25:29 +0200 | [diff] [blame] | 237 | mtebc(PB0CR, CONFIG_SYS_EBC_PB0CR); |
| 238 | mtebc(PB0AP, CONFIG_SYS_EBC_PB0AP); |
Stefan Roese | 42fbddd | 2006-09-07 11:51:23 +0200 | [diff] [blame] | 239 | #endif |
| 240 | |
Heiko Schocher | 3ec4366 | 2006-12-21 17:17:02 +0100 | [diff] [blame] | 241 | return 0; |
Stefan Roese | 42fbddd | 2006-09-07 11:51:23 +0200 | [diff] [blame] | 242 | } |