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wdenk4989f872004-03-14 15:06:13 +00001/*
2 * (C) Copyright 2003
3 * Texas Instruments.
4 * Kshitij Gupta <kshitij@ti.com>
5 * Configuation settings for the TI OMAP Innovator board.
6 *
7 * (C) Copyright 2004
8 * ARM Ltd.
9 * Philippe Robin, <philippe.robin@arm.com>
10 * Configuration for Versatile PB.
11 *
12 * See file CREDITS for list of people who contributed to this
13 * project.
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 * MA 02111-1307 USA
29 */
30
31#ifndef __CONFIG_H
32#define __CONFIG_H
33
34/*
35 * High Level Configuration Options
36 * (easy to change)
37 */
Jean-Christophe PLAGNIOL-VILLARDfdf1cb82009-06-20 11:02:17 +020038#define CONFIG_ARM926EJS 1 /* This is an arm926ejs CPU core */
wdenk4989f872004-03-14 15:06:13 +000039#define CONFIG_VERSATILE 1 /* in Versatile Platform Board */
Jean-Christophe PLAGNIOL-VILLARDfdf1cb82009-06-20 11:02:17 +020040#define CONFIG_ARCH_VERSATILE 1 /* Specifically, a Versatile */
wdenk4989f872004-03-14 15:06:13 +000041
Jean-Christophe PLAGNIOL-VILLARD1b5092d2009-05-02 11:53:49 +020042#ifndef CONFIG_ARCH_VERSATILE_AB /* AB */
43#define CONFIG_ARCH_VERSATILE_PB /* Versatile PB is default */
44#endif
45
Jean-Christophe PLAGNIOL-VILLARDfdf1cb82009-06-20 11:02:17 +020046#define CONFIG_SYS_MEMTEST_START 0x100000
47#define CONFIG_SYS_MEMTEST_END 0x10000000
48#define CONFIG_SYS_HZ (1000000 / 256)
49#define CONFIG_SYS_TIMERBASE 0x101E2000 /* Timer 0 and 1 base */
wdenk4989f872004-03-14 15:06:13 +000050
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020051#define CONFIG_SYS_TIMER_INTERVAL 10000
Jean-Christophe PLAGNIOL-VILLARDfdf1cb82009-06-20 11:02:17 +020052#define CONFIG_SYS_TIMER_RELOAD (CONFIG_SYS_TIMER_INTERVAL >> 4)
53#define CONFIG_SYS_TIMER_CTRL 0x84 /* Enable, Clock / 16 */
wdenk4989f872004-03-14 15:06:13 +000054
55/*
56 * control registers
57 */
Jean-Christophe PLAGNIOL-VILLARDfdf1cb82009-06-20 11:02:17 +020058#define VERSATILE_SCTL_BASE 0x101E0000 /* System controller */
wdenk4989f872004-03-14 15:06:13 +000059
60/*
61 * System controller bit assignment
62 */
63#define VERSATILE_REFCLK 0
64#define VERSATILE_TIMCLK 1
65
66#define VERSATILE_TIMER1_EnSel 15
67#define VERSATILE_TIMER2_EnSel 17
68#define VERSATILE_TIMER3_EnSel 19
69#define VERSATILE_TIMER4_EnSel 21
70
Jean-Christophe PLAGNIOL-VILLARDfdf1cb82009-06-20 11:02:17 +020071#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
wdenk4989f872004-03-14 15:06:13 +000072#define CONFIG_SETUP_MEMORY_TAGS 1
Jean-Christophe PLAGNIOL-VILLARDfdf1cb82009-06-20 11:02:17 +020073#define CONFIG_MISC_INIT_R 1
wdenk4989f872004-03-14 15:06:13 +000074/*
75 * Size of malloc() pool
76 */
Jean-Christophe PLAGNIOL-VILLARDfdf1cb82009-06-20 11:02:17 +020077#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024)
wdenk4989f872004-03-14 15:06:13 +000078
79/*
80 * Hardware drivers
81 */
82
Ben Warren0fd6aae2009-10-04 22:37:03 -070083#define CONFIG_NET_MULTI
84#define CONFIG_SMC91111
wdenk4989f872004-03-14 15:06:13 +000085#define CONFIG_SMC_USE_32_BIT
Wolfgang Denka1be4762008-05-20 16:00:29 +020086#define CONFIG_SMC91111_BASE 0x10010000
wdenk4989f872004-03-14 15:06:13 +000087#undef CONFIG_SMC91111_EXT_PHY
88
89/*
90 * NS16550 Configuration
91 */
Andreas Engel0813b122008-09-08 14:30:53 +020092#define CONFIG_PL011_SERIAL
wdenkda04a8b2004-08-02 23:22:59 +000093#define CONFIG_PL011_CLOCK 24000000
Jean-Christophe PLAGNIOL-VILLARDfdf1cb82009-06-20 11:02:17 +020094#define CONFIG_PL01x_PORTS \
95 {(void *)CONFIG_SYS_SERIAL0, \
96 (void *)CONFIG_SYS_SERIAL1 }
wdenk4989f872004-03-14 15:06:13 +000097#define CONFIG_CONS_INDEX 0
wdenkda04a8b2004-08-02 23:22:59 +000098
Jean-Christophe PLAGNIOL-VILLARDfdf1cb82009-06-20 11:02:17 +020099#define CONFIG_BAUDRATE 38400
100#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200101#define CONFIG_SYS_SERIAL0 0x101F1000
102#define CONFIG_SYS_SERIAL1 0x101F2000
wdenk4989f872004-03-14 15:06:13 +0000103
Jon Loeliger03bfcb92007-07-04 22:33:46 -0500104/*
105 * Command line configuration.
106 */
Jean-Christophe PLAGNIOL-VILLARDfdf1cb82009-06-20 11:02:17 +0200107#define CONFIG_CMD_BDI
Jon Loeliger03bfcb92007-07-04 22:33:46 -0500108#define CONFIG_CMD_DHCP
Jean-Christophe PLAGNIOL-VILLARDfdf1cb82009-06-20 11:02:17 +0200109#define CONFIG_CMD_FLASH
Jon Loeliger03bfcb92007-07-04 22:33:46 -0500110#define CONFIG_CMD_IMI
Jean-Christophe PLAGNIOL-VILLARDfdf1cb82009-06-20 11:02:17 +0200111#define CONFIG_CMD_MEMORY
Jon Loeliger03bfcb92007-07-04 22:33:46 -0500112#define CONFIG_CMD_NET
113#define CONFIG_CMD_PING
Mike Frysinger78dcaf42009-01-28 19:08:14 -0500114#define CONFIG_CMD_SAVEENV
wdenk4989f872004-03-14 15:06:13 +0000115
Jon Loeligerc6d535a2007-07-09 21:57:31 -0500116/*
117 * BOOTP options
118 */
Jean-Christophe PLAGNIOL-VILLARDfdf1cb82009-06-20 11:02:17 +0200119#define CONFIG_BOOTP_BOOTPATH
Jon Loeligerc6d535a2007-07-09 21:57:31 -0500120#define CONFIG_BOOTP_GATEWAY
121#define CONFIG_BOOTP_HOSTNAME
Jean-Christophe PLAGNIOL-VILLARDfdf1cb82009-06-20 11:02:17 +0200122#define CONFIG_BOOTP_SUBNETMASK
wdenk4989f872004-03-14 15:06:13 +0000123
124#define CONFIG_BOOTDELAY 2
Jean-Christophe PLAGNIOL-VILLARDfdf1cb82009-06-20 11:02:17 +0200125#define CONFIG_BOOTARGS "root=/dev/nfs mem=128M ip=dhcp "\
126 "netdev=25,0,0xf1010000,0xf1010010,eth0"
wdenk4989f872004-03-14 15:06:13 +0000127
128/*
129 * Static configuration when assigning fixed address
130 */
Jean-Christophe PLAGNIOL-VILLARDfdf1cb82009-06-20 11:02:17 +0200131#define CONFIG_BOOTFILE "/tftpboot/uImage" /* file to load */
wdenk4989f872004-03-14 15:06:13 +0000132
133/*
134 * Miscellaneous configurable options
135 */
Jean-Christophe PLAGNIOL-VILLARDfdf1cb82009-06-20 11:02:17 +0200136#define CONFIG_SYS_LONGHELP /* undef to save memory */
Jean-Christophe PLAGNIOL-VILLARDfdf1cb82009-06-20 11:02:17 +0200137#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Jean-Christophe PLAGNIOL-VILLARD1b5092d2009-05-02 11:53:49 +0200138/* Monitor Command Prompt */
139#ifdef CONFIG_ARCH_VERSATILE_AB
140# define CONFIG_SYS_PROMPT "VersatileAB # "
141#else
142# define CONFIG_SYS_PROMPT "VersatilePB # "
143#endif
wdenk4989f872004-03-14 15:06:13 +0000144/* Print Buffer Size */
Jean-Christophe PLAGNIOL-VILLARDfdf1cb82009-06-20 11:02:17 +0200145#define CONFIG_SYS_PBSIZE \
146 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
147#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
148#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenk4989f872004-03-14 15:06:13 +0000149
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200150#define CONFIG_SYS_LOAD_ADDR 0x7fc0 /* default load address */
wdenk4989f872004-03-14 15:06:13 +0000151
152/*-----------------------------------------------------------------------
153 * Stack sizes
154 *
155 * The stack sizes are set up in start.S using the settings below
156 */
Jean-Christophe PLAGNIOL-VILLARDfdf1cb82009-06-20 11:02:17 +0200157#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
wdenk4989f872004-03-14 15:06:13 +0000158#ifdef CONFIG_USE_IRQ
Jean-Christophe PLAGNIOL-VILLARDfdf1cb82009-06-20 11:02:17 +0200159#define CONFIG_STACKSIZE_IRQ (4 * 1024) /* IRQ stack */
160#define CONFIG_STACKSIZE_FIQ (4 * 1024) /* FIQ stack */
wdenk4989f872004-03-14 15:06:13 +0000161#endif
162
163/*-----------------------------------------------------------------------
164 * Physical Memory Map
165 */
Jean-Christophe PLAGNIOL-VILLARDfdf1cb82009-06-20 11:02:17 +0200166#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
167#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */
168#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */
Jean-Christophe PLAGNIOL-VILLARD6ebf7e92009-05-02 11:53:50 +0200169#define PHYS_FLASH_SIZE 0x04000000 /* 64MB */
wdenk4989f872004-03-14 15:06:13 +0000170
171/*-----------------------------------------------------------------------
172 * FLASH and environment organization
173 */
Jean-Christophe PLAGNIOL-VILLARD6ebf7e92009-05-02 11:53:50 +0200174/*
175 * Use the CFI flash driver for ease of use
176 */
177#define CONFIG_SYS_FLASH_CFI
178#define CONFIG_FLASH_CFI_DRIVER
179#define CONFIG_ENV_IS_IN_FLASH 1
180/*
181 * System control register
182 */
Jean-Christophe PLAGNIOL-VILLARDfdf1cb82009-06-20 11:02:17 +0200183#define VERSATILE_SYS_BASE 0x10000000
184#define VERSATILE_SYS_FLASH_OFFSET 0x4C
185#define VERSATILE_FLASHCTRL \
186 (VERSATILE_SYS_BASE + VERSATILE_SYS_FLASH_OFFSET)
187/* Enable writing to flash */
188#define VERSATILE_FLASHPROG_FLVPPEN (1 << 0)
wdenkc3919532004-10-11 22:51:13 +0000189
wdenk4989f872004-03-14 15:06:13 +0000190/* timeout values are in ticks */
Jean-Christophe PLAGNIOL-VILLARD6ebf7e92009-05-02 11:53:50 +0200191#define CONFIG_SYS_FLASH_ERASE_TOUT (2 * CONFIG_SYS_HZ) /* Erase Timeout */
192#define CONFIG_SYS_FLASH_WRITE_TOUT (2 * CONFIG_SYS_HZ) /* Write Timeout */
193
194/*
195 * Note that CONFIG_SYS_MAX_FLASH_SECT allows for a parameter block
196 * i.e.
197 * the bottom "sector" (bottom boot), or top "sector"
198 * (top boot), is a seperate erase region divided into
199 * 4 (equal) smaller sectors. This, notionally, allows
200 * quicker erase/rewrire of the most frequently changed
201 * area......
202 * CONFIG_SYS_MAX_FLASH_SECT is padded up to a multiple of 4
203 */
wdenk4989f872004-03-14 15:06:13 +0000204
Jean-Christophe PLAGNIOL-VILLARD6ebf7e92009-05-02 11:53:50 +0200205#ifdef CONFIG_ARCH_VERSATILE_AB
206#define FLASH_SECTOR_SIZE 0x00020000 /* 128 KB sectors */
207#define CONFIG_ENV_SECT_SIZE (2 * FLASH_SECTOR_SIZE)
208#define CONFIG_SYS_MAX_FLASH_SECT (520)
209#endif
wdenk4989f872004-03-14 15:06:13 +0000210
Jean-Christophe PLAGNIOL-VILLARD6ebf7e92009-05-02 11:53:50 +0200211#ifdef CONFIG_ARCH_VERSATILE_PB /* Versatile PB is default */
212#define FLASH_SECTOR_SIZE 0x00040000 /* 256 KB sectors */
213#define CONFIG_ENV_SECT_SIZE FLASH_SECTOR_SIZE
214#define CONFIG_SYS_MAX_FLASH_SECT (260)
215#endif
216
217#define CONFIG_SYS_FLASH_BASE 0x34000000
218#define CONFIG_SYS_MAX_FLASH_BANKS 1
219
220#define CONFIG_SYS_MONITOR_LEN (4 * CONFIG_ENV_SECT_SIZE)
221
222/* The ARM Boot Monitor is shipped in the lowest sector of flash */
223
224#define FLASH_TOP (CONFIG_SYS_FLASH_BASE + PHYS_FLASH_SIZE)
225#define CONFIG_ENV_SIZE 8192
226#define CONFIG_ENV_ADDR (FLASH_TOP - CONFIG_ENV_SECT_SIZE)
227#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
228#define CONFIG_SYS_MONITOR_BASE (CONFIG_ENV_ADDR - CONFIG_SYS_MONITOR_LEN)
229
230#define CONFIG_SYS_FLASH_PROTECTION /* The devices have real protection */
231#define CONFIG_SYS_FLASH_EMPTY_INFO /* flinfo indicates empty blocks */
wdenkc3919532004-10-11 22:51:13 +0000232
Jean-Christophe PLAGNIOL-VILLARD6ebf7e92009-05-02 11:53:50 +0200233#endif /* __CONFIG_H */