Liu Gang | b452693 | 2012-03-08 00:33:16 +0000 | [diff] [blame] | 1 | ------------------------------ |
| 2 | SRIO Boot on Corenet Platforms |
| 3 | ------------------------------ |
| 4 | |
| 5 | For some PowerPC processors with SRIO interface, boot location can be configured |
| 6 | to SRIO by RCW. The processor booting from SRIO can do without flash for u-boot |
| 7 | image, ucode and ENV. All the images can be fetched from another processor's |
| 8 | memory space by SRIO link connected between them. |
| 9 | |
| 10 | This document describes the processes based on an example implemented on P4080DS |
| 11 | platforms and a RCW example with boot from SRIO configuration. |
| 12 | |
| 13 | Environment of the SRIO boot: |
| 14 | a) Master and slave can be SOCs in one board or SOCs in separate boards. |
| 15 | b) They are connected with SRIO links, whether 1x or 4x, and directly or |
| 16 | through switch system. |
| 17 | c) Only Master has NorFlash for booting, and all the Master's and Slave's |
| 18 | U-Boot images, UCodes will be stored in this flash. |
| 19 | d) Slave has its own EEPROM for RCW and PBI. |
| 20 | e) Slave's RCW should configure the SerDes for SRIO boot port, set the boot |
| 21 | location to SRIO, and holdoff all the cores if needed. |
| 22 | |
| 23 | ---------- ----------- ----------- |
| 24 | | | | | | | |
| 25 | | | | | | | |
| 26 | | NorFlash|<----->| Master | SRIO | Slave |<---->[EEPROM] |
| 27 | | | | |<===========>| | |
| 28 | | | | | | | |
| 29 | ---------- ----------- ----------- |
| 30 | |
| 31 | The example based on P4080DS platform: |
| 32 | Two P4080DS platforms can be used to implement the boot from SRIO. Their SRIO |
| 33 | ports 0 will be connected directly and will be used for the boot from SRIO. |
| 34 | |
| 35 | 1. Slave's RCW example for boot from SRIO port 0 and core 0 not in holdoff. |
| 36 | 00000000: aa55 aa55 010e 0100 0c58 0000 0000 0000 |
| 37 | 00000010: 1818 1818 0000 8888 7440 4000 0000 2000 |
| 38 | 00000020: f400 0000 0100 0000 0000 0000 0000 0000 |
| 39 | 00000030: 0000 0000 0083 0000 0000 0000 0000 0000 |
| 40 | 00000040: 0000 0000 0000 0000 0813 8040 698b 93fe |
| 41 | |
| 42 | 2. Slave's RCW example for boot from SRIO port 0 and all cores in holdoff. |
| 43 | 00000000: aa55 aa55 010e 0100 0c58 0000 0000 0000 |
| 44 | 00000010: 1818 1818 0000 8888 7440 4000 0000 2000 |
| 45 | 00000020: f440 0000 0100 0000 0000 0000 0000 0000 |
| 46 | 00000030: 0000 0000 0083 0000 0000 0000 0000 0000 |
| 47 | 00000040: 0000 0000 0000 0000 0813 8040 063c 778f |
| 48 | |
| 49 | 3. Sequence in Step by Step. |
| 50 | a) Update RCW for slave with boot from SRIO port 0 configuration. |
| 51 | b) Program slave's U-Boot image, UCode, and ENV parameters into master's |
| 52 | NorFlash. |
| 53 | c) Start up master and it will boot up normally from its NorFlash. |
| 54 | Then, it will finish necessary configurations for slave's boot from |
| 55 | SRIO port 0. |
| 56 | d) Master will set inbound SRIO windows covered slave's U-Boot image stored |
| 57 | in master's NorFlash. |
| 58 | e) Master will set an inbound SRIO window covered slave's UCode stored in |
| 59 | master's NorFlash. |
| 60 | f) Master will set an inbound SRIO window covered slave's ENV stored in |
| 61 | master's NorFlash. |
| 62 | g) If need to release slave's core, master will set outbound SRIO windows |
| 63 | in order to configure slave's registers for the core's releasing. |
| 64 | h) If all cores of slave in holdoff, slave should be powered on before all |
| 65 | the above master's steps, and wait to be released by master. If not all |
| 66 | cores in holdoff, that means core 0 will start up normally, slave should |
| 67 | be powered on after all the above master's steps. In the startup phase |
| 68 | of the slave from SRIO, it will finish some necessary configurations. |
| 69 | i) Slave will set a specific TLB entry for the boot process. |
| 70 | j) Slave will set a LAW entry with the TargetID SRIO port 0 for the boot. |
| 71 | k) Slave will set a specific TLB entry in order to fetch UCode and ENV |
| 72 | from master. |
| 73 | l) Slave will set a LAW entry with the TargetID SRIO port 0 for UCode and ENV. |
| 74 | |
| 75 | How to use this feature: |
| 76 | To use this feature, you need to focus three points. |
| 77 | |
| 78 | 1. Slave's RCW with SRIO boot configurations, and all cores in holdoff |
| 79 | configurations if needed. |
| 80 | Please refer to the examples given above. |
| 81 | |
| 82 | 2. U-Boot image's compilation. |
| 83 | For master, U-Boot image should be generated specifically by |
| 84 | |
| 85 | make xxxx_SRIOBOOT_MASTER_config. |
| 86 | |
| 87 | For example, master U-Boot image used on P4080DS should be compiled with |
| 88 | |
| 89 | make P4080DS_SRIOBOOT_MASTER_config. |
| 90 | |
| 91 | For slave, U-Boot image should be generated specifically by |
| 92 | |
| 93 | make xxxx_SRIOBOOT_SLAVE_config. |
| 94 | |
| 95 | For example, slave U-Boot image used on P4080DS should be compiled with |
| 96 | |
| 97 | make P4080DS_SRIOBOOT_SLAVE_config. |
| 98 | |
| 99 | 3. Necessary modifications based on a specific environment. |
| 100 | For a specific environment, the SRIO port for boot, the addresses of the |
| 101 | slave's U-Boot image, UCode, ENV stored in master's NorFlash, and any other |
| 102 | configurations can be modified in the file: |
| 103 | include/configs/corenet_ds.h. |