Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
York Sun | 56cc3db | 2014-09-08 12:20:00 -0700 | [diff] [blame] | 2 | /* |
Mingkai Hu | 0e58b51 | 2015-10-26 19:47:50 +0800 | [diff] [blame] | 3 | * Copyright 2014-2015 Freescale Semiconductor, Inc. |
York Sun | 56cc3db | 2014-09-08 12:20:00 -0700 | [diff] [blame] | 4 | */ |
| 5 | |
| 6 | #include <common.h> |
Simon Glass | 970b61e | 2019-11-14 12:57:09 -0700 | [diff] [blame] | 7 | #include <cpu_func.h> |
Simon Glass | 2dc9c34 | 2020-05-10 11:40:01 -0600 | [diff] [blame] | 8 | #include <image.h> |
Michael Walle | 24d116d | 2020-06-01 21:53:25 +0200 | [diff] [blame] | 9 | #include <log.h> |
Simon Glass | 274e0b0 | 2020-05-10 11:39:56 -0600 | [diff] [blame] | 10 | #include <asm/cache.h> |
Simon Glass | 3ba929a | 2020-10-30 21:38:53 -0600 | [diff] [blame] | 11 | #include <asm/global_data.h> |
York Sun | 56cc3db | 2014-09-08 12:20:00 -0700 | [diff] [blame] | 12 | #include <asm/io.h> |
| 13 | #include <asm/system.h> |
Mingkai Hu | 0e58b51 | 2015-10-26 19:47:50 +0800 | [diff] [blame] | 14 | #include <asm/arch/mp.h> |
| 15 | #include <asm/arch/soc.h> |
Simon Glass | dbd7954 | 2020-05-10 11:40:11 -0600 | [diff] [blame] | 16 | #include <linux/delay.h> |
Priyanka Jain | 9a27670 | 2016-11-17 12:29:56 +0530 | [diff] [blame] | 17 | #include "cpu.h" |
| 18 | #include <asm/arch-fsl-layerscape/soc.h> |
Michael Walle | c251f5b | 2020-06-01 21:53:34 +0200 | [diff] [blame] | 19 | #include <efi_loader.h> |
York Sun | 56cc3db | 2014-09-08 12:20:00 -0700 | [diff] [blame] | 20 | |
| 21 | DECLARE_GLOBAL_DATA_PTR; |
| 22 | |
| 23 | void *get_spin_tbl_addr(void) |
| 24 | { |
Michael Walle | c251f5b | 2020-06-01 21:53:34 +0200 | [diff] [blame] | 25 | /* the spin table is at the beginning */ |
| 26 | return secondary_boot_code_start; |
York Sun | 56cc3db | 2014-09-08 12:20:00 -0700 | [diff] [blame] | 27 | } |
| 28 | |
Alison Wang | 876c7e1 | 2016-11-10 10:49:04 +0800 | [diff] [blame] | 29 | void update_os_arch_secondary_cores(uint8_t os_arch) |
| 30 | { |
| 31 | u64 *table = get_spin_tbl_addr(); |
| 32 | int i; |
| 33 | |
Alison Wang | a6231fe | 2017-06-08 16:15:14 +0800 | [diff] [blame] | 34 | for (i = 1; i < CONFIG_MAX_CPUS; i++) { |
| 35 | if (os_arch == IH_ARCH_DEFAULT) |
| 36 | table[i * WORDS_PER_SPIN_TABLE_ENTRY + |
| 37 | SPIN_TABLE_ELEM_ARCH_COMP_IDX] = OS_ARCH_SAME; |
| 38 | else |
| 39 | table[i * WORDS_PER_SPIN_TABLE_ENTRY + |
| 40 | SPIN_TABLE_ELEM_ARCH_COMP_IDX] = OS_ARCH_DIFF; |
| 41 | } |
Alison Wang | 876c7e1 | 2016-11-10 10:49:04 +0800 | [diff] [blame] | 42 | } |
| 43 | |
Priyanka Jain | 9a27670 | 2016-11-17 12:29:56 +0530 | [diff] [blame] | 44 | #ifdef CONFIG_FSL_LSCH3 |
Michael Walle | 319f1a3 | 2020-06-01 21:53:32 +0200 | [diff] [blame] | 45 | static void wake_secondary_core_n(int cluster, int core, int cluster_cores) |
Priyanka Jain | 9a27670 | 2016-11-17 12:29:56 +0530 | [diff] [blame] | 46 | { |
| 47 | struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); |
| 48 | struct ccsr_reset __iomem *rst = (void *)(CONFIG_SYS_FSL_RST_ADDR); |
| 49 | u32 mpidr = 0; |
| 50 | |
| 51 | mpidr = ((cluster << 8) | core); |
| 52 | /* |
| 53 | * mpidr_el1 register value of core which needs to be released |
| 54 | * is written to scratchrw[6] register |
| 55 | */ |
| 56 | gur_out32(&gur->scratchrw[6], mpidr); |
| 57 | asm volatile("dsb st" : : : "memory"); |
| 58 | rst->brrl |= 1 << ((cluster * cluster_cores) + core); |
| 59 | asm volatile("dsb st" : : : "memory"); |
| 60 | /* |
| 61 | * scratchrw[6] register value is polled |
| 62 | * when the value becomes zero, this means that this core is up |
| 63 | * and running, next core can be released now |
| 64 | */ |
| 65 | while (gur_in32(&gur->scratchrw[6]) != 0) |
| 66 | ; |
| 67 | } |
| 68 | #endif |
| 69 | |
Mingkai Hu | 0e58b51 | 2015-10-26 19:47:50 +0800 | [diff] [blame] | 70 | int fsl_layerscape_wake_seconday_cores(void) |
York Sun | 56cc3db | 2014-09-08 12:20:00 -0700 | [diff] [blame] | 71 | { |
| 72 | struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); |
Hou Zhiqiang | c7098fa | 2015-10-26 19:47:57 +0800 | [diff] [blame] | 73 | #ifdef CONFIG_FSL_LSCH3 |
York Sun | 56cc3db | 2014-09-08 12:20:00 -0700 | [diff] [blame] | 74 | struct ccsr_reset __iomem *rst = (void *)(CONFIG_SYS_FSL_RST_ADDR); |
Priyanka Jain | 9a27670 | 2016-11-17 12:29:56 +0530 | [diff] [blame] | 75 | u32 svr, ver, cluster, type; |
| 76 | int j = 0, cluster_cores = 0; |
Hou Zhiqiang | c7098fa | 2015-10-26 19:47:57 +0800 | [diff] [blame] | 77 | #elif defined(CONFIG_FSL_LSCH2) |
| 78 | struct ccsr_scfg __iomem *scfg = (void *)(CONFIG_SYS_FSL_SCFG_ADDR); |
| 79 | #endif |
York Sun | 56cc3db | 2014-09-08 12:20:00 -0700 | [diff] [blame] | 80 | u32 cores, cpu_up_mask = 1; |
| 81 | int i, timeout = 10; |
Michael Walle | bd7e4ee | 2020-06-01 21:53:31 +0200 | [diff] [blame] | 82 | u64 *table; |
Michael Walle | 661c602 | 2020-06-01 21:53:35 +0200 | [diff] [blame] | 83 | #ifdef CONFIG_EFI_LOADER |
| 84 | u64 reloc_addr = U32_MAX; |
| 85 | efi_status_t ret; |
| 86 | #endif |
York Sun | 56cc3db | 2014-09-08 12:20:00 -0700 | [diff] [blame] | 87 | |
York Sun | 77a1097 | 2015-03-20 19:28:08 -0700 | [diff] [blame] | 88 | #ifdef COUNTER_FREQUENCY_REAL |
| 89 | /* update for secondary cores */ |
| 90 | __real_cntfrq = COUNTER_FREQUENCY_REAL; |
| 91 | flush_dcache_range((unsigned long)&__real_cntfrq, |
| 92 | (unsigned long)&__real_cntfrq + 8); |
| 93 | #endif |
| 94 | |
Michael Walle | 661c602 | 2020-06-01 21:53:35 +0200 | [diff] [blame] | 95 | #ifdef CONFIG_EFI_LOADER |
| 96 | /* |
| 97 | * EFI will reserve 64kb for its runtime services. This will probably |
| 98 | * overlap with our spin table code, which is why we have to relocate |
| 99 | * it. |
| 100 | * Keep this after the __real_cntfrq update, so we have it when we |
| 101 | * copy the complete section here. |
| 102 | */ |
| 103 | ret = efi_allocate_pages(EFI_ALLOCATE_MAX_ADDRESS, |
| 104 | EFI_RESERVED_MEMORY_TYPE, |
| 105 | efi_size_in_pages(secondary_boot_code_size), |
| 106 | &reloc_addr); |
| 107 | if (ret == EFI_SUCCESS) { |
| 108 | debug("Relocating spin table from %llx to %llx (size %lx)\n", |
| 109 | (u64)secondary_boot_code_start, reloc_addr, |
| 110 | secondary_boot_code_size); |
| 111 | memcpy((void *)reloc_addr, secondary_boot_code_start, |
| 112 | secondary_boot_code_size); |
| 113 | flush_dcache_range(reloc_addr, |
| 114 | reloc_addr + secondary_boot_code_size); |
| 115 | |
| 116 | /* set new entry point for secondary cores */ |
| 117 | secondary_boot_addr += (void *)reloc_addr - |
| 118 | secondary_boot_code_start; |
| 119 | flush_dcache_range((unsigned long)&secondary_boot_addr, |
| 120 | (unsigned long)&secondary_boot_addr + 8); |
| 121 | |
| 122 | /* this will be used to reserve the memory */ |
| 123 | secondary_boot_code_start = (void *)reloc_addr; |
| 124 | } |
| 125 | #endif |
| 126 | |
York Sun | 56cc3db | 2014-09-08 12:20:00 -0700 | [diff] [blame] | 127 | cores = cpu_mask(); |
| 128 | /* Clear spin table so that secondary processors |
| 129 | * observe the correct value after waking up from wfe. |
| 130 | */ |
Michael Walle | bd7e4ee | 2020-06-01 21:53:31 +0200 | [diff] [blame] | 131 | table = get_spin_tbl_addr(); |
York Sun | 56cc3db | 2014-09-08 12:20:00 -0700 | [diff] [blame] | 132 | memset(table, 0, CONFIG_MAX_CPUS*SPIN_TABLE_ELEM_SIZE); |
| 133 | flush_dcache_range((unsigned long)table, |
| 134 | (unsigned long)table + |
| 135 | (CONFIG_MAX_CPUS*SPIN_TABLE_ELEM_SIZE)); |
| 136 | |
Michael Walle | 24d116d | 2020-06-01 21:53:25 +0200 | [diff] [blame] | 137 | debug("Waking secondary cores to start from %lx\n", gd->relocaddr); |
Mingkai Hu | 0e58b51 | 2015-10-26 19:47:50 +0800 | [diff] [blame] | 138 | |
Hou Zhiqiang | c7098fa | 2015-10-26 19:47:57 +0800 | [diff] [blame] | 139 | #ifdef CONFIG_FSL_LSCH3 |
Mingkai Hu | 0e58b51 | 2015-10-26 19:47:50 +0800 | [diff] [blame] | 140 | gur_out32(&gur->bootlocptrh, (u32)(gd->relocaddr >> 32)); |
| 141 | gur_out32(&gur->bootlocptrl, (u32)gd->relocaddr); |
Priyanka Jain | 9a27670 | 2016-11-17 12:29:56 +0530 | [diff] [blame] | 142 | |
| 143 | svr = gur_in32(&gur->svr); |
| 144 | ver = SVR_SOC_VER(svr); |
| 145 | if (ver == SVR_LS2080A || ver == SVR_LS2085A) { |
| 146 | gur_out32(&gur->scratchrw[6], 1); |
| 147 | asm volatile("dsb st" : : : "memory"); |
| 148 | rst->brrl = cores; |
| 149 | asm volatile("dsb st" : : : "memory"); |
| 150 | } else { |
| 151 | /* |
| 152 | * Release the cores out of reset one-at-a-time to avoid |
| 153 | * power spikes |
| 154 | */ |
| 155 | i = 0; |
| 156 | cluster = in_le32(&gur->tp_cluster[i].lower); |
| 157 | for (j = 0; j < TP_INIT_PER_CLUSTER; j++) { |
| 158 | type = initiator_type(cluster, j); |
| 159 | if (type && |
| 160 | TP_ITYP_TYPE(type) == TP_ITYP_TYPE_ARM) |
| 161 | cluster_cores++; |
| 162 | } |
| 163 | |
| 164 | do { |
| 165 | cluster = in_le32(&gur->tp_cluster[i].lower); |
| 166 | for (j = 0; j < TP_INIT_PER_CLUSTER; j++) { |
| 167 | type = initiator_type(cluster, j); |
| 168 | if (type && |
| 169 | TP_ITYP_TYPE(type) == TP_ITYP_TYPE_ARM) |
| 170 | wake_secondary_core_n(i, j, |
| 171 | cluster_cores); |
| 172 | } |
| 173 | i++; |
| 174 | } while ((cluster & TP_CLUSTER_EOC) != TP_CLUSTER_EOC); |
| 175 | } |
Hou Zhiqiang | c7098fa | 2015-10-26 19:47:57 +0800 | [diff] [blame] | 176 | #elif defined(CONFIG_FSL_LSCH2) |
| 177 | scfg_out32(&scfg->scratchrw[0], (u32)(gd->relocaddr >> 32)); |
| 178 | scfg_out32(&scfg->scratchrw[1], (u32)gd->relocaddr); |
| 179 | asm volatile("dsb st" : : : "memory"); |
| 180 | gur_out32(&gur->brrl, cores); |
| 181 | asm volatile("dsb st" : : : "memory"); |
York Sun | 56cc3db | 2014-09-08 12:20:00 -0700 | [diff] [blame] | 182 | |
Hou Zhiqiang | c7098fa | 2015-10-26 19:47:57 +0800 | [diff] [blame] | 183 | /* Bootup online cores */ |
| 184 | scfg_out32(&scfg->corebcr, cores); |
| 185 | #endif |
York Sun | 56cc3db | 2014-09-08 12:20:00 -0700 | [diff] [blame] | 186 | /* This is needed as a precautionary measure. |
| 187 | * If some code before this has accidentally released the secondary |
| 188 | * cores then the pre-bootloader code will trap them in a "wfe" unless |
| 189 | * the scratchrw[6] is set. In this case we need a sev here to get these |
| 190 | * cores moving again. |
| 191 | */ |
| 192 | asm volatile("sev"); |
| 193 | |
| 194 | while (timeout--) { |
| 195 | flush_dcache_range((unsigned long)table, (unsigned long)table + |
| 196 | CONFIG_MAX_CPUS * 64); |
| 197 | for (i = 1; i < CONFIG_MAX_CPUS; i++) { |
| 198 | if (table[i * WORDS_PER_SPIN_TABLE_ENTRY + |
| 199 | SPIN_TABLE_ELEM_STATUS_IDX]) |
| 200 | cpu_up_mask |= 1 << i; |
| 201 | } |
| 202 | if (hweight32(cpu_up_mask) == hweight32(cores)) |
| 203 | break; |
| 204 | udelay(10); |
| 205 | } |
| 206 | if (timeout <= 0) { |
Michael Walle | 24d116d | 2020-06-01 21:53:25 +0200 | [diff] [blame] | 207 | printf("CPU: Failed to bring up some cores (mask 0x%x)\n", |
| 208 | cores ^ cpu_up_mask); |
York Sun | 56cc3db | 2014-09-08 12:20:00 -0700 | [diff] [blame] | 209 | return 1; |
| 210 | } |
Michael Walle | 24d116d | 2020-06-01 21:53:25 +0200 | [diff] [blame] | 211 | printf("CPU: %d cores online\n", hweight32(cores)); |
York Sun | 56cc3db | 2014-09-08 12:20:00 -0700 | [diff] [blame] | 212 | |
| 213 | return 0; |
| 214 | } |
| 215 | |
| 216 | int is_core_valid(unsigned int core) |
| 217 | { |
| 218 | return !!((1 << core) & cpu_mask()); |
| 219 | } |
| 220 | |
York Sun | ed7fbe3 | 2016-09-13 12:40:30 -0700 | [diff] [blame] | 221 | static int is_pos_valid(unsigned int pos) |
| 222 | { |
| 223 | return !!((1 << pos) & cpu_pos_mask()); |
| 224 | } |
| 225 | |
Arnab Basu | 0cb1942 | 2015-01-06 13:18:41 -0800 | [diff] [blame] | 226 | int is_core_online(u64 cpu_id) |
| 227 | { |
Michael Walle | bd7e4ee | 2020-06-01 21:53:31 +0200 | [diff] [blame] | 228 | u64 *table = get_spin_tbl_addr(); |
Arnab Basu | 0cb1942 | 2015-01-06 13:18:41 -0800 | [diff] [blame] | 229 | int pos = id_to_core(cpu_id); |
Michael Walle | bd7e4ee | 2020-06-01 21:53:31 +0200 | [diff] [blame] | 230 | table += pos * WORDS_PER_SPIN_TABLE_ENTRY; |
Arnab Basu | 0cb1942 | 2015-01-06 13:18:41 -0800 | [diff] [blame] | 231 | return table[SPIN_TABLE_ELEM_STATUS_IDX] == 1; |
| 232 | } |
| 233 | |
Michal Simek | 1669e18 | 2018-06-13 08:56:31 +0200 | [diff] [blame] | 234 | int cpu_reset(u32 nr) |
York Sun | 56cc3db | 2014-09-08 12:20:00 -0700 | [diff] [blame] | 235 | { |
| 236 | puts("Feature is not implemented.\n"); |
| 237 | |
| 238 | return 0; |
| 239 | } |
| 240 | |
Michal Simek | 1669e18 | 2018-06-13 08:56:31 +0200 | [diff] [blame] | 241 | int cpu_disable(u32 nr) |
York Sun | 56cc3db | 2014-09-08 12:20:00 -0700 | [diff] [blame] | 242 | { |
| 243 | puts("Feature is not implemented.\n"); |
| 244 | |
| 245 | return 0; |
| 246 | } |
| 247 | |
York Sun | ed7fbe3 | 2016-09-13 12:40:30 -0700 | [diff] [blame] | 248 | static int core_to_pos(int nr) |
York Sun | 56cc3db | 2014-09-08 12:20:00 -0700 | [diff] [blame] | 249 | { |
York Sun | ed7fbe3 | 2016-09-13 12:40:30 -0700 | [diff] [blame] | 250 | u32 cores = cpu_pos_mask(); |
York Sun | 56cc3db | 2014-09-08 12:20:00 -0700 | [diff] [blame] | 251 | int i, count = 0; |
| 252 | |
| 253 | if (nr == 0) { |
| 254 | return 0; |
| 255 | } else if (nr >= hweight32(cores)) { |
| 256 | puts("Not a valid core number.\n"); |
| 257 | return -1; |
| 258 | } |
| 259 | |
| 260 | for (i = 1; i < 32; i++) { |
York Sun | ed7fbe3 | 2016-09-13 12:40:30 -0700 | [diff] [blame] | 261 | if (is_pos_valid(i)) { |
York Sun | 56cc3db | 2014-09-08 12:20:00 -0700 | [diff] [blame] | 262 | count++; |
| 263 | if (count == nr) |
| 264 | break; |
| 265 | } |
| 266 | } |
| 267 | |
York Sun | ed7fbe3 | 2016-09-13 12:40:30 -0700 | [diff] [blame] | 268 | if (count != nr) |
| 269 | return -1; |
| 270 | |
| 271 | return i; |
York Sun | 56cc3db | 2014-09-08 12:20:00 -0700 | [diff] [blame] | 272 | } |
| 273 | |
Michal Simek | 1669e18 | 2018-06-13 08:56:31 +0200 | [diff] [blame] | 274 | int cpu_status(u32 nr) |
York Sun | 56cc3db | 2014-09-08 12:20:00 -0700 | [diff] [blame] | 275 | { |
Michael Walle | bd7e4ee | 2020-06-01 21:53:31 +0200 | [diff] [blame] | 276 | u64 *table = get_spin_tbl_addr(); |
York Sun | 56cc3db | 2014-09-08 12:20:00 -0700 | [diff] [blame] | 277 | int pos; |
| 278 | |
| 279 | if (nr == 0) { |
York Sun | 56cc3db | 2014-09-08 12:20:00 -0700 | [diff] [blame] | 280 | printf("table base @ 0x%p\n", table); |
| 281 | } else { |
| 282 | pos = core_to_pos(nr); |
| 283 | if (pos < 0) |
| 284 | return -1; |
Michael Walle | bd7e4ee | 2020-06-01 21:53:31 +0200 | [diff] [blame] | 285 | table += pos * WORDS_PER_SPIN_TABLE_ENTRY; |
York Sun | 56cc3db | 2014-09-08 12:20:00 -0700 | [diff] [blame] | 286 | printf("table @ 0x%p\n", table); |
| 287 | printf(" addr - 0x%016llx\n", |
| 288 | table[SPIN_TABLE_ELEM_ENTRY_ADDR_IDX]); |
| 289 | printf(" status - 0x%016llx\n", |
| 290 | table[SPIN_TABLE_ELEM_STATUS_IDX]); |
| 291 | printf(" lpid - 0x%016llx\n", |
| 292 | table[SPIN_TABLE_ELEM_LPID_IDX]); |
| 293 | } |
| 294 | |
| 295 | return 0; |
| 296 | } |
| 297 | |
Simon Glass | ed38aef | 2020-05-10 11:40:03 -0600 | [diff] [blame] | 298 | int cpu_release(u32 nr, int argc, char *const argv[]) |
York Sun | 56cc3db | 2014-09-08 12:20:00 -0700 | [diff] [blame] | 299 | { |
| 300 | u64 boot_addr; |
Michael Walle | bd7e4ee | 2020-06-01 21:53:31 +0200 | [diff] [blame] | 301 | u64 *table = get_spin_tbl_addr(); |
York Sun | 56cc3db | 2014-09-08 12:20:00 -0700 | [diff] [blame] | 302 | int pos; |
| 303 | |
| 304 | pos = core_to_pos(nr); |
| 305 | if (pos <= 0) |
| 306 | return -1; |
| 307 | |
| 308 | table += pos * WORDS_PER_SPIN_TABLE_ENTRY; |
| 309 | boot_addr = simple_strtoull(argv[0], NULL, 16); |
| 310 | table[SPIN_TABLE_ELEM_ENTRY_ADDR_IDX] = boot_addr; |
| 311 | flush_dcache_range((unsigned long)table, |
| 312 | (unsigned long)table + SPIN_TABLE_ELEM_SIZE); |
| 313 | asm volatile("dsb st"); |
Michael Walle | 576f6850 | 2020-06-01 21:53:24 +0200 | [diff] [blame] | 314 | |
York Sun | 89c717c | 2015-11-12 12:38:21 -0800 | [diff] [blame] | 315 | /* |
Michael Walle | 576f6850 | 2020-06-01 21:53:24 +0200 | [diff] [blame] | 316 | * The secondary CPUs polling the spin-table above for a non-zero |
| 317 | * value. To save power "wfe" is called. Thus call "sev" here to |
| 318 | * wake the CPUs and let them check the spin-table again (see |
| 319 | * slave_cpu loop in lowlevel.S) |
York Sun | 89c717c | 2015-11-12 12:38:21 -0800 | [diff] [blame] | 320 | */ |
| 321 | asm volatile("sev"); |
York Sun | 56cc3db | 2014-09-08 12:20:00 -0700 | [diff] [blame] | 322 | |
| 323 | return 0; |
| 324 | } |