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Kumar Gala3ab0b2d2008-08-12 11:13:08 -05001/*
2 * Copyright 2007-2008 Freescale Semiconductor, Inc.
3 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
23/*
24 * mpc8572ds board configuration file
25 *
26 */
27#ifndef __CONFIG_H
28#define __CONFIG_H
29
Kumar Gala0d899ab2009-09-10 16:23:45 -050030#ifdef CONFIG_MK_36BIT
31#define CONFIG_PHYS_64BIT
32#endif
33
Kumar Gala3ab0b2d2008-08-12 11:13:08 -050034/* High Level Configuration Options */
35#define CONFIG_BOOKE 1 /* BOOKE */
36#define CONFIG_E500 1 /* BOOKE e500 family */
37#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */
38#define CONFIG_MPC8572 1
39#define CONFIG_MPC8572DS 1
40#define CONFIG_MP 1 /* support multiple processors */
Kumar Gala3ab0b2d2008-08-12 11:13:08 -050041
Kumar Gala1a5ba5f2009-01-23 14:22:13 -060042#define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */
Kumar Gala3ab0b2d2008-08-12 11:13:08 -050043#define CONFIG_PCI 1 /* Enable PCI/PCIE */
44#define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */
45#define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */
46#define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */
47#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
48#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
Kumar Gala7738d5c2008-10-21 11:33:58 -050049#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
Kumar Gala3ab0b2d2008-08-12 11:13:08 -050050
51#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
52
53#define CONFIG_TSEC_ENET /* tsec ethernet support */
54#define CONFIG_ENV_OVERWRITE
55
Kumar Gala3ab0b2d2008-08-12 11:13:08 -050056#ifndef __ASSEMBLY__
57extern unsigned long get_board_sys_clk(unsigned long dummy);
58extern unsigned long get_board_ddr_clk(unsigned long dummy);
59#endif
60#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */
61#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk(0) /* ddrclk for MPC85xx */
Haiying Wangbcf35e52008-10-03 12:37:41 -040062#define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */
Kumar Gala3ab0b2d2008-08-12 11:13:08 -050063#define CONFIG_GET_CLK_FROM_ICS307 /* decode sysclk and ddrclk freq
64 from ICS307 instead of switches */
65
66/*
67 * These can be toggled for performance analysis, otherwise use default.
68 */
69#define CONFIG_L2_CACHE /* toggle L2 cache */
70#define CONFIG_BTB /* toggle branch predition */
Kumar Gala3ab0b2d2008-08-12 11:13:08 -050071
72#define CONFIG_ENABLE_36BIT_PHYS 1
73
Kumar Galae0f97412009-01-23 14:22:14 -060074#ifdef CONFIG_PHYS_64BIT
75#define CONFIG_ADDR_MAP 1
76#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
77#endif
78
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020079#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */
80#define CONFIG_SYS_MEMTEST_END 0x7fffffff
Kumar Gala3ab0b2d2008-08-12 11:13:08 -050081#define CONFIG_PANIC_HANG /* do not reset board on panic */
82
83/*
84 * Base addresses -- Note these are effective addresses where the
85 * actual resources get mapped (not physical addresses)
86 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020087#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
88#define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */
Kumar Galae0f97412009-01-23 14:22:14 -060089#ifdef CONFIG_PHYS_64BIT
90#define CONFIG_SYS_CCSRBAR_PHYS 0xfffe00000ull /* physical addr of CCSRBAR */
91#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020092#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */
Kumar Galae0f97412009-01-23 14:22:14 -060093#endif
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020094#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
Kumar Gala3ab0b2d2008-08-12 11:13:08 -050095
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020096#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_CCSRBAR+0x8000)
97#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR+0x9000)
98#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000)
Kumar Gala3ab0b2d2008-08-12 11:13:08 -050099
100/* DDR Setup */
Kumar Gala6630ffb2009-02-06 09:56:35 -0600101#define CONFIG_VERY_BIG_RAM
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500102#define CONFIG_FSL_DDR2
103#undef CONFIG_FSL_DDR_INTERACTIVE
104#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
105#define CONFIG_DDR_SPD
106#undef CONFIG_DDR_DLL
107
Dave Liud3ca1242008-10-28 17:53:38 +0800108#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500109#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
110
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200111#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
112#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500113
114#define CONFIG_NUM_DDR_CONTROLLERS 2
115#define CONFIG_DIMM_SLOTS_PER_CTLR 1
116#define CONFIG_CHIP_SELECTS_PER_CTRL 2
117
118/* I2C addresses of SPD EEPROMs */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200119#define CONFIG_SYS_SPD_BUS_NUM 1 /* SPD EEPROMS locate on I2C bus 1 */
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500120#define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */
121#define SPD_EEPROM_ADDRESS2 0x52 /* CTLR 1 DIMM 0 */
122
123/* These are used when DDR doesn't use SPD. */
Dave Liu6b78b162008-11-28 20:16:58 +0800124#define CONFIG_SYS_SDRAM_SIZE 512 /* DDR is 512MB */
125#define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F
126#define CONFIG_SYS_DDR_CS0_CONFIG 0x80010202 /* Enable, no interleaving */
127#define CONFIG_SYS_DDR_TIMING_3 0x00020000
128#define CONFIG_SYS_DDR_TIMING_0 0x00260802
129#define CONFIG_SYS_DDR_TIMING_1 0x626b2634
130#define CONFIG_SYS_DDR_TIMING_2 0x062874cf
131#define CONFIG_SYS_DDR_MODE_1 0x00440462
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200132#define CONFIG_SYS_DDR_MODE_2 0x00000000
Dave Liu6b78b162008-11-28 20:16:58 +0800133#define CONFIG_SYS_DDR_INTERVAL 0x0c300100
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200134#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
Dave Liu6b78b162008-11-28 20:16:58 +0800135#define CONFIG_SYS_DDR_CLK_CTRL 0x00800000
136#define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200137#define CONFIG_SYS_DDR_OCD_STATUS 0x00000000
Dave Liu6b78b162008-11-28 20:16:58 +0800138#define CONFIG_SYS_DDR_CONTROL 0xc3000008 /* Type = DDR2 */
139#define CONFIG_SYS_DDR_CONTROL2 0x24400000
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500140
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200141#define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d
142#define CONFIG_SYS_DDR_ERR_DIS 0x00000000
143#define CONFIG_SYS_DDR_SBE 0x00010000
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500144
145/*
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500146 * Make sure required options are set
147 */
148#ifndef CONFIG_SPD_EEPROM
149#error ("CONFIG_SPD_EEPROM is required")
150#endif
151
152#undef CONFIG_CLOCKS_IN_MHZ
153
154/*
155 * Memory map
156 *
157 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
158 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable
159 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable
160 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable
161 *
162 * Localbus cacheable (TBD)
163 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable
164 *
165 * Localbus non-cacheable
166 * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable
167 * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable
Wolfgang Denk82f15f32008-11-02 16:14:22 +0100168 * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500169 * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0
170 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
171 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
172 */
173
174/*
175 * Local Bus Definitions
176 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200177#define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */
Kumar Galae0f97412009-01-23 14:22:14 -0600178#ifdef CONFIG_PHYS_64BIT
179#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
180#else
Kumar Gala4be8b572008-12-02 14:19:34 -0600181#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
Kumar Galae0f97412009-01-23 14:22:14 -0600182#endif
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500183
Kumar Gala4be8b572008-12-02 14:19:34 -0600184#define CONFIG_SYS_BR0_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | BR_PS_16 | BR_V)
185#define CONFIG_SYS_OR0_PRELIM 0xf8000ff7
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500186
Kumar Gala4be8b572008-12-02 14:19:34 -0600187#define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
188#define CONFIG_SYS_OR1_PRELIM 0xf8000ff7
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500189
Kumar Galae0f97412009-01-23 14:22:14 -0600190#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200191#define CONFIG_SYS_FLASH_QUIET_TEST
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500192#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
193
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200194#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
195#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
196#undef CONFIG_SYS_FLASH_CHECKSUM
197#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
198#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500199
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200200#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500201
202#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200203#define CONFIG_SYS_FLASH_CFI
204#define CONFIG_SYS_FLASH_EMPTY_INFO
205#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500206
207#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
208
209#define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */
210#define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
Kumar Galae0f97412009-01-23 14:22:14 -0600211#ifdef CONFIG_PHYS_64BIT
212#define PIXIS_BASE_PHYS 0xfffdf0000ull
213#else
Kumar Gala0f492b42008-12-02 14:19:33 -0600214#define PIXIS_BASE_PHYS PIXIS_BASE
Kumar Galae0f97412009-01-23 14:22:14 -0600215#endif
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500216
Kumar Gala0f492b42008-12-02 14:19:33 -0600217#define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200218#define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500219
220#define PIXIS_ID 0x0 /* Board ID at offset 0 */
221#define PIXIS_VER 0x1 /* Board version at offset 1 */
222#define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */
223#define PIXIS_CSR 0x3 /* PIXIS General control/status register */
224#define PIXIS_RST 0x4 /* PIXIS Reset Control register */
225#define PIXIS_PWR 0x5 /* PIXIS Power status register */
226#define PIXIS_AUX 0x6 /* Auxiliary 1 register */
227#define PIXIS_SPD 0x7 /* Register for SYSCLK speed */
228#define PIXIS_AUX2 0x8 /* Auxiliary 2 register */
229#define PIXIS_VCTL 0x10 /* VELA Control Register */
230#define PIXIS_VSTAT 0x11 /* VELA Status Register */
231#define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */
232#define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */
233#define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */
234#define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */
Kumar Galae21db032009-07-14 22:42:01 -0500235#define PIXIS_VBOOT_LBMAP 0xc0 /* VBOOT - CFG_LBMAP */
236#define PIXIS_VBOOT_LBMAP_NOR0 0x00 /* cfg_lbmap - boot from NOR 0 */
237#define PIXIS_VBOOT_LBMAP_PJET 0x01 /* cfg_lbmap - boot from projet */
238#define PIXIS_VBOOT_LBMAP_NAND 0x02 /* cfg_lbmap - boot from NAND */
239#define PIXIS_VBOOT_LBMAP_NOR1 0x03 /* cfg_lbmap - boot from NOR 1 */
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500240#define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */
241#define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
242#define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */
243#define PIXIS_VSYSCLK0 0x1C /* VELA SYSCLK0 Register */
244#define PIXIS_VSYSCLK1 0x1D /* VELA SYSCLK1 Register */
245#define PIXIS_VSYSCLK2 0x1E /* VELA SYSCLK2 Register */
246#define PIXIS_VDDRCLK0 0x1F /* VELA DDRCLK0 Register */
247#define PIXIS_VDDRCLK1 0x20 /* VELA DDRCLK1 Register */
248#define PIXIS_VDDRCLK2 0x21 /* VELA DDRCLK2 Register */
249#define PIXIS_VWATCH 0x24 /* Watchdog Register */
250#define PIXIS_LED 0x25 /* LED Register */
251
252/* old pixis referenced names */
253#define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
254#define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200255#define CONFIG_SYS_PIXIS_VBOOT_MASK 0xc0
Liu Yuc49bce42008-10-10 11:40:59 +0800256#define PIXIS_VSPEED2_TSEC1SER 0x8
257#define PIXIS_VSPEED2_TSEC2SER 0x4
258#define PIXIS_VSPEED2_TSEC3SER 0x2
259#define PIXIS_VSPEED2_TSEC4SER 0x1
260#define PIXIS_VCFGEN1_TSEC1SER 0x20
261#define PIXIS_VCFGEN1_TSEC2SER 0x20
262#define PIXIS_VCFGEN1_TSEC3SER 0x20
263#define PIXIS_VCFGEN1_TSEC4SER 0x20
264#define PIXIS_VSPEED2_MASK (PIXIS_VSPEED2_TSEC1SER \
265 | PIXIS_VSPEED2_TSEC2SER \
266 | PIXIS_VSPEED2_TSEC3SER \
267 | PIXIS_VSPEED2_TSEC4SER)
268#define PIXIS_VCFGEN1_MASK (PIXIS_VCFGEN1_TSEC1SER \
269 | PIXIS_VCFGEN1_TSEC2SER \
270 | PIXIS_VCFGEN1_TSEC3SER \
271 | PIXIS_VCFGEN1_TSEC4SER)
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500272
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200273#define CONFIG_SYS_INIT_RAM_LOCK 1
274#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
275#define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500276
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200277#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
278#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
279#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500280
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200281#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
282#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500283
Haiying Wang9fce13f2008-10-29 13:32:59 -0400284#define CONFIG_SYS_NAND_BASE 0xffa00000
Kumar Galae0f97412009-01-23 14:22:14 -0600285#ifdef CONFIG_PHYS_64BIT
286#define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
287#else
Haiying Wang9fce13f2008-10-29 13:32:59 -0400288#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
Kumar Galae0f97412009-01-23 14:22:14 -0600289#endif
Haiying Wang9fce13f2008-10-29 13:32:59 -0400290#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\
291 CONFIG_SYS_NAND_BASE + 0x40000, \
292 CONFIG_SYS_NAND_BASE + 0x80000,\
293 CONFIG_SYS_NAND_BASE + 0xC0000}
294#define CONFIG_SYS_MAX_NAND_DEVICE 4
Haiying Wang9fce13f2008-10-29 13:32:59 -0400295#define CONFIG_MTD_NAND_VERIFY_WRITE
Wolfgang Denk82f15f32008-11-02 16:14:22 +0100296#define CONFIG_CMD_NAND 1
297#define CONFIG_NAND_FSL_ELBC 1
Haiying Wang9fce13f2008-10-29 13:32:59 -0400298#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
299
300/* NAND flash config */
Kumar Galaf55afa02009-01-23 14:22:12 -0600301#define CONFIG_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
Wolfgang Denk82f15f32008-11-02 16:14:22 +0100302 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
303 | BR_PS_8 /* Port Size = 8 bit */ \
304 | BR_MS_FCM /* MSEL = FCM */ \
305 | BR_V) /* valid */
306#define CONFIG_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
307 | OR_FCM_PGS /* Large Page*/ \
308 | OR_FCM_CSCT \
309 | OR_FCM_CST \
310 | OR_FCM_CHT \
311 | OR_FCM_SCY_1 \
312 | OR_FCM_TRLX \
313 | OR_FCM_EHTR)
Haiying Wang9fce13f2008-10-29 13:32:59 -0400314
315#define CONFIG_SYS_BR2_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */
316#define CONFIG_SYS_OR2_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
317
Kumar Galaf55afa02009-01-23 14:22:12 -0600318#define CONFIG_SYS_BR4_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x40000))\
Wolfgang Denk82f15f32008-11-02 16:14:22 +0100319 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
320 | BR_PS_8 /* Port Size = 8 bit */ \
321 | BR_MS_FCM /* MSEL = FCM */ \
322 | BR_V) /* valid */
323#define CONFIG_SYS_OR4_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
Kumar Galaf55afa02009-01-23 14:22:12 -0600324#define CONFIG_SYS_BR5_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x80000))\
Wolfgang Denk82f15f32008-11-02 16:14:22 +0100325 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
326 | BR_PS_8 /* Port Size = 8 bit */ \
327 | BR_MS_FCM /* MSEL = FCM */ \
328 | BR_V) /* valid */
329#define CONFIG_SYS_OR5_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
Haiying Wang9fce13f2008-10-29 13:32:59 -0400330
Kumar Galaf55afa02009-01-23 14:22:12 -0600331#define CONFIG_SYS_BR6_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0xc0000))\
Wolfgang Denk82f15f32008-11-02 16:14:22 +0100332 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
333 | BR_PS_8 /* Port Size = 8 bit */ \
334 | BR_MS_FCM /* MSEL = FCM */ \
335 | BR_V) /* valid */
336#define CONFIG_SYS_OR6_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
Haiying Wang9fce13f2008-10-29 13:32:59 -0400337
338
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500339/* Serial Port - controlled on board with jumper J8
340 * open - index 2
341 * shorted - index 1
342 */
343#define CONFIG_CONS_INDEX 1
344#undef CONFIG_SERIAL_SOFTWARE_FIFO
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200345#define CONFIG_SYS_NS16550
346#define CONFIG_SYS_NS16550_SERIAL
347#define CONFIG_SYS_NS16550_REG_SIZE 1
348#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500349
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200350#define CONFIG_SYS_BAUDRATE_TABLE \
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500351 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
352
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200353#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
354#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500355
356/* Use the HUSH parser */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200357#define CONFIG_SYS_HUSH_PARSER
358#ifdef CONFIG_SYS_HUSH_PARSER
359#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500360#endif
361
362/*
363 * Pass open firmware flat tree
364 */
365#define CONFIG_OF_LIBFDT 1
366#define CONFIG_OF_BOARD_SETUP 1
367#define CONFIG_OF_STDOUT_VIA_ALIAS 1
368
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500369/* new uImage format support */
370#define CONFIG_FIT 1
371#define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */
372
373/* I2C */
374#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
375#define CONFIG_HARD_I2C /* I2C with hardware support */
376#undef CONFIG_SOFT_I2C /* I2C bit-banged */
Haiying Wangbd319c72008-10-03 11:46:59 -0400377#define CONFIG_I2C_MULTI_BUS
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200378#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
379#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
380#define CONFIG_SYS_I2C_SLAVE 0x7F
381#define CONFIG_SYS_I2C_NOPROBES {{0,0x29}}/* Don't probe these addrs */
382#define CONFIG_SYS_I2C_OFFSET 0x3000
383#define CONFIG_SYS_I2C2_OFFSET 0x3100
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500384
385/*
Haiying Wang374130f2008-10-03 11:47:30 -0400386 * I2C2 EEPROM
387 */
388#define CONFIG_ID_EEPROM
389#ifdef CONFIG_ID_EEPROM
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200390#define CONFIG_SYS_I2C_EEPROM_NXID
Haiying Wang374130f2008-10-03 11:47:30 -0400391#endif
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200392#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
393#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
394#define CONFIG_SYS_EEPROM_BUS_NUM 1
Haiying Wang374130f2008-10-03 11:47:30 -0400395
396/*
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500397 * General PCI
398 * Memory space is mapped 1-1, but I/O space must start from 0.
399 */
400
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500401/* controller 3, direct to uli, tgtid 3, Base address 8000 */
Kumar Galaef43b6e2008-12-02 16:08:39 -0600402#define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000
Kumar Galae0f97412009-01-23 14:22:14 -0600403#ifdef CONFIG_PHYS_64BIT
Kumar Galae1cb3db2009-06-18 08:39:42 -0500404#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
Kumar Galae0f97412009-01-23 14:22:14 -0600405#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull
406#else
Kumar Gala2275d0e2009-02-09 22:03:05 -0600407#define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000
Kumar Galaef43b6e2008-12-02 16:08:39 -0600408#define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000
Kumar Galae0f97412009-01-23 14:22:14 -0600409#endif
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200410#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
Kumar Gala60ff4642008-12-02 16:08:40 -0600411#define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000
Kumar Gala64bb6d12008-12-02 16:08:37 -0600412#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
Kumar Galae0f97412009-01-23 14:22:14 -0600413#ifdef CONFIG_PHYS_64BIT
414#define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull
415#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200416#define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000
Kumar Galae0f97412009-01-23 14:22:14 -0600417#endif
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200418#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500419
420/* controller 2, Slot 2, tgtid 2, Base address 9000 */
Kumar Galaef43b6e2008-12-02 16:08:39 -0600421#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
Kumar Galae0f97412009-01-23 14:22:14 -0600422#ifdef CONFIG_PHYS_64BIT
Kumar Galae1cb3db2009-06-18 08:39:42 -0500423#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
Kumar Galae0f97412009-01-23 14:22:14 -0600424#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
425#else
Kumar Gala2275d0e2009-02-09 22:03:05 -0600426#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
Kumar Galaef43b6e2008-12-02 16:08:39 -0600427#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
Kumar Galae0f97412009-01-23 14:22:14 -0600428#endif
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200429#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
Kumar Gala60ff4642008-12-02 16:08:40 -0600430#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
Kumar Gala64bb6d12008-12-02 16:08:37 -0600431#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
Kumar Galae0f97412009-01-23 14:22:14 -0600432#ifdef CONFIG_PHYS_64BIT
433#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
434#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200435#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
Kumar Galae0f97412009-01-23 14:22:14 -0600436#endif
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200437#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500438
439/* controller 1, Slot 1, tgtid 1, Base address a000 */
Kumar Galaef43b6e2008-12-02 16:08:39 -0600440#define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
Kumar Galae0f97412009-01-23 14:22:14 -0600441#ifdef CONFIG_PHYS_64BIT
Kumar Galae1cb3db2009-06-18 08:39:42 -0500442#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
Kumar Galae0f97412009-01-23 14:22:14 -0600443#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull
444#else
Kumar Gala2275d0e2009-02-09 22:03:05 -0600445#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
Kumar Galaef43b6e2008-12-02 16:08:39 -0600446#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000
Kumar Galae0f97412009-01-23 14:22:14 -0600447#endif
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200448#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
Kumar Gala60ff4642008-12-02 16:08:40 -0600449#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000
Kumar Gala64bb6d12008-12-02 16:08:37 -0600450#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
Kumar Galae0f97412009-01-23 14:22:14 -0600451#ifdef CONFIG_PHYS_64BIT
452#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull
453#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200454#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000
Kumar Galae0f97412009-01-23 14:22:14 -0600455#endif
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200456#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500457
458#if defined(CONFIG_PCI)
459
460/*PCIE video card used*/
Kumar Gala60ff4642008-12-02 16:08:40 -0600461#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500462
463/* video */
464#define CONFIG_VIDEO
465
466#if defined(CONFIG_VIDEO)
467#define CONFIG_BIOSEMU
468#define CONFIG_CFB_CONSOLE
469#define CONFIG_VIDEO_SW_CURSOR
470#define CONFIG_VGA_AS_SINGLE_DEVICE
471#define CONFIG_ATI_RADEON_FB
472#define CONFIG_VIDEO_LOGO
473/*#define CONFIG_CONSOLE_CURSOR*/
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200474#define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500475#endif
476
477#define CONFIG_NET_MULTI
478#define CONFIG_PCI_PNP /* do pci plug-and-play */
479
480#undef CONFIG_EEPRO100
481#undef CONFIG_TULIP
482#undef CONFIG_RTL8139
483
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500484#ifndef CONFIG_PCI_PNP
Kumar Gala64bb6d12008-12-02 16:08:37 -0600485 #define PCI_ENET0_IOADDR CONFIG_SYS_PCIE3_IO_BUS
486 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCIE3_IO_BUS
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500487 #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */
488#endif
489
490#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
491#define CONFIG_DOS_PARTITION
492#define CONFIG_SCSI_AHCI
493
494#ifdef CONFIG_SCSI_AHCI
495#define CONFIG_SATA_ULI5288
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200496#define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
497#define CONFIG_SYS_SCSI_MAX_LUN 1
498#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
499#define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500500#endif /* SCSI */
501
502#endif /* CONFIG_PCI */
503
504
505#if defined(CONFIG_TSEC_ENET)
506
507#ifndef CONFIG_NET_MULTI
508#define CONFIG_NET_MULTI 1
509#endif
510
511#define CONFIG_MII 1 /* MII PHY management */
512#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
513#define CONFIG_TSEC1 1
514#define CONFIG_TSEC1_NAME "eTSEC1"
515#define CONFIG_TSEC2 1
516#define CONFIG_TSEC2_NAME "eTSEC2"
517#define CONFIG_TSEC3 1
518#define CONFIG_TSEC3_NAME "eTSEC3"
519#define CONFIG_TSEC4 1
520#define CONFIG_TSEC4_NAME "eTSEC4"
521
Liu Yuc49bce42008-10-10 11:40:59 +0800522#define CONFIG_PIXIS_SGMII_CMD
523#define CONFIG_FSL_SGMII_RISER 1
524#define SGMII_RISER_PHY_OFFSET 0x1c
525
526#ifdef CONFIG_FSL_SGMII_RISER
527#define CONFIG_SYS_TBIPA_VALUE 0x10 /* avoid conflict with eTSEC4 paddr */
528#endif
529
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500530#define TSEC1_PHY_ADDR 0
531#define TSEC2_PHY_ADDR 1
532#define TSEC3_PHY_ADDR 2
533#define TSEC4_PHY_ADDR 3
534
535#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
536#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
537#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
538#define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
539
540#define TSEC1_PHYIDX 0
541#define TSEC2_PHYIDX 0
542#define TSEC3_PHYIDX 0
543#define TSEC4_PHYIDX 0
544
545#define CONFIG_ETHPRIME "eTSEC1"
546
547#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
548#endif /* CONFIG_TSEC_ENET */
549
550/*
551 * Environment
552 */
Jean-Christophe PLAGNIOL-VILLARD53db4cd2008-09-10 22:48:04 +0200553#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200554#if CONFIG_SYS_MONITOR_BASE > 0xfff80000
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200555#define CONFIG_ENV_ADDR 0xfff80000
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500556#else
Haiying Wang68623782008-10-31 05:06:14 -0500557#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500558#endif
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200559#define CONFIG_ENV_SIZE 0x2000
560#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500561
562#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200563#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500564
565/*
566 * Command line configuration.
567 */
568#include <config_cmd_default.h>
569
570#define CONFIG_CMD_IRQ
571#define CONFIG_CMD_PING
572#define CONFIG_CMD_I2C
573#define CONFIG_CMD_MII
574#define CONFIG_CMD_ELF
Kumar Gala489675d2008-09-22 23:40:42 -0500575#define CONFIG_CMD_IRQ
576#define CONFIG_CMD_SETEXPR
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500577
578#if defined(CONFIG_PCI)
579#define CONFIG_CMD_PCI
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500580#define CONFIG_CMD_NET
581#define CONFIG_CMD_SCSI
582#define CONFIG_CMD_EXT2
583#endif
584
585#undef CONFIG_WATCHDOG /* watchdog disabled */
586
587/*
588 * Miscellaneous configurable options
589 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200590#define CONFIG_SYS_LONGHELP /* undef to save memory */
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500591#define CONFIG_CMDLINE_EDITING /* Command-line editing */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200592#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
593#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500594#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200595#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500596#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200597#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500598#endif
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200599#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
600#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
601#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
602#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500603
604/*
605 * For booting Linux, the board info and command line data
Kumar Gala1535d812009-07-15 08:54:50 -0500606 * have to be in the first 16 MB of memory, since this is
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500607 * the maximum mapped by the Linux kernel during initialization.
608 */
Kumar Gala1535d812009-07-15 08:54:50 -0500609#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500610
611/*
612 * Internal Definitions
613 *
614 * Boot Flags
615 */
616#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
617#define BOOTFLAG_WARM 0x02 /* Software reboot */
618
619#if defined(CONFIG_CMD_KGDB)
620#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
621#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
622#endif
623
624/*
625 * Environment Configuration
626 */
627
628/* The mac addresses for all ethernet interface */
629#if defined(CONFIG_TSEC_ENET)
630#define CONFIG_HAS_ETH0
631#define CONFIG_ETHADDR 00:E0:0C:02:00:FD
632#define CONFIG_HAS_ETH1
633#define CONFIG_ETH1ADDR 00:E0:0C:02:01:FD
634#define CONFIG_HAS_ETH2
635#define CONFIG_ETH2ADDR 00:E0:0C:02:02:FD
636#define CONFIG_HAS_ETH3
637#define CONFIG_ETH3ADDR 00:E0:0C:02:03:FD
638#endif
639
640#define CONFIG_IPADDR 192.168.1.254
641
642#define CONFIG_HOSTNAME unknown
643#define CONFIG_ROOTPATH /opt/nfsroot
644#define CONFIG_BOOTFILE uImage
645#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
646
647#define CONFIG_SERVERIP 192.168.1.1
648#define CONFIG_GATEWAYIP 192.168.1.1
649#define CONFIG_NETMASK 255.255.255.0
650
651/* default location for tftp and bootm */
652#define CONFIG_LOADADDR 1000000
653
654#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
655#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
656
657#define CONFIG_BAUDRATE 115200
658
659#define CONFIG_EXTRA_ENV_SETTINGS \
Haiying Wangbcf35e52008-10-03 12:37:41 -0400660 "memctl_intlv_ctl=2\0" \
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500661 "netdev=eth0\0" \
662 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
663 "tftpflash=tftpboot $loadaddr $uboot; " \
664 "protect off " MK_STR(TEXT_BASE) " +$filesize; " \
665 "erase " MK_STR(TEXT_BASE) " +$filesize; " \
666 "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \
667 "protect on " MK_STR(TEXT_BASE) " +$filesize; " \
668 "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \
669 "consoledev=ttyS0\0" \
670 "ramdiskaddr=2000000\0" \
671 "ramdiskfile=8572ds/ramdisk.uboot\0" \
672 "fdtaddr=c00000\0" \
673 "fdtfile=8572ds/mpc8572ds.dtb\0" \
674 "bdev=sda3\0"
675
676#define CONFIG_HDBOOT \
677 "setenv bootargs root=/dev/$bdev rw " \
678 "console=$consoledev,$baudrate $othbootargs;" \
679 "tftp $loadaddr $bootfile;" \
680 "tftp $fdtaddr $fdtfile;" \
681 "bootm $loadaddr - $fdtaddr"
682
683#define CONFIG_NFSBOOTCOMMAND \
684 "setenv bootargs root=/dev/nfs rw " \
685 "nfsroot=$serverip:$rootpath " \
686 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
687 "console=$consoledev,$baudrate $othbootargs;" \
688 "tftp $loadaddr $bootfile;" \
689 "tftp $fdtaddr $fdtfile;" \
690 "bootm $loadaddr - $fdtaddr"
691
692#define CONFIG_RAMBOOTCOMMAND \
693 "setenv bootargs root=/dev/ram rw " \
694 "console=$consoledev,$baudrate $othbootargs;" \
695 "tftp $ramdiskaddr $ramdiskfile;" \
696 "tftp $loadaddr $bootfile;" \
697 "tftp $fdtaddr $fdtfile;" \
698 "bootm $loadaddr $ramdiskaddr $fdtaddr"
699
700#define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
701
702#endif /* __CONFIG_H */