| Mike Frysinger | 66c4cf4 | 2008-02-04 19:26:55 -0500 | [diff] [blame] | 1 | /* |
| 2 | * EBIU Masks |
| 3 | */ |
| 4 | |
| 5 | #ifndef __BFIN_PERIPHERAL_EBIU__ |
| 6 | #define __BFIN_PERIPHERAL_EBIU__ |
| 7 | |
| 8 | /* EBIU_AMGCTL Masks */ |
| 9 | #define AMCKEN 0x0001 /* Enable CLKOUT */ |
| 10 | #define AMBEN_NONE 0x0000 /* All Banks Disabled */ |
| 11 | #define AMBEN_B0 0x0002 /* Enable Asynchronous Memory Bank 0 only */ |
| 12 | #define AMBEN_B0_B1 0x0004 /* Enable Asynchronous Memory Banks 0 & 1 only */ |
| 13 | #define AMBEN_B0_B1_B2 0x0006 /* Enable Asynchronous Memory Banks 0,/ 1, and 2 */ |
| 14 | #define AMBEN_ALL 0x0008 /* Enable Asynchronous Memory Banks (all) 0, 1, 2, and 3 */ |
| 15 | #define B0_PEN 0x0010 /* Enable 16-bit packing Bank 0 */ |
| 16 | #define B1_PEN 0x0020 /* Enable 16-bit packing Bank 1 */ |
| 17 | #define B2_PEN 0x0040 /* Enable 16-bit packing Bank 2 */ |
| 18 | #define B3_PEN 0x0080 /* Enable 16-bit packing Bank 3 */ |
| 19 | #define CDPRIO 0x0100 /* Core has priority over DMA for external accesses */ |
| 20 | |
| 21 | /* EBIU_AMGCTL Bit Positions */ |
| 22 | #define AMCKEN_P 0x00000000 /* Enable CLKOUT */ |
| 23 | #define AMBEN_P0 0x00000001 /* Asynchronous Memory Enable, 000 - banks 0-3 disabled, 001 - Bank 0 enabled */ |
| 24 | #define AMBEN_P1 0x00000002 /* Asynchronous Memory Enable, 010 - banks 0&1 enabled, 011 - banks 0-3 enabled */ |
| 25 | #define AMBEN_P2 0x00000003 /* Asynchronous Memory Enable, 1xx - All banks (bank 0, 1, 2, and 3) enabled */ |
| 26 | #define B0_PEN_P 0x00000004 /* Enable 16-bit packing Bank 0 */ |
| 27 | #define B1_PEN_P 0x00000005 /* Enable 16-bit packing Bank 1 */ |
| 28 | #define B2_PEN_P 0x00000006 /* Enable 16-bit packing Bank 2 */ |
| 29 | #define B3_PEN_P 0x00000007 /* Enable 16-bit packing Bank 3 */ |
| 30 | #define CDPRIO_P 0x00000008 /* Core has priority over DMA for external accesses */ |
| 31 | |
| 32 | /* EBIU_AMBCTL0 Masks */ |
| 33 | #define B0RDYEN 0x00000001 /* Bank 0 RDY Enable, 0=disable, 1=enable */ |
| 34 | #define B0RDYPOL 0x00000002 /* Bank 0 RDY Active high, 0=active low, 1=active high */ |
| 35 | #define B0TT_1 0x00000004 /* Bank 0 Transition Time from Read to Write = 1 cycle */ |
| 36 | #define B0TT_2 0x00000008 /* Bank 0 Transition Time from Read to Write = 2 cycles */ |
| 37 | #define B0TT_3 0x0000000C /* Bank 0 Transition Time from Read to Write = 3 cycles */ |
| 38 | #define B0TT_4 0x00000000 /* Bank 0 Transition Time from Read to Write = 4 cycles */ |
| 39 | #define B0ST_1 0x00000010 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=1 cycle */ |
| 40 | #define B0ST_2 0x00000020 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=2 cycles */ |
| 41 | #define B0ST_3 0x00000030 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=3 cycles */ |
| 42 | #define B0ST_4 0x00000000 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=4 cycles */ |
| 43 | #define B0HT_1 0x00000040 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 1 cycle */ |
| 44 | #define B0HT_2 0x00000080 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 2 cycles */ |
| 45 | #define B0HT_3 0x000000C0 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 3 cycles */ |
| 46 | #define B0HT_0 0x00000000 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 0 cycles */ |
| 47 | #define B0RAT_1 0x00000100 /* Bank 0 Read Access Time = 1 cycle */ |
| 48 | #define B0RAT_2 0x00000200 /* Bank 0 Read Access Time = 2 cycles */ |
| 49 | #define B0RAT_3 0x00000300 /* Bank 0 Read Access Time = 3 cycles */ |
| 50 | #define B0RAT_4 0x00000400 /* Bank 0 Read Access Time = 4 cycles */ |
| 51 | #define B0RAT_5 0x00000500 /* Bank 0 Read Access Time = 5 cycles */ |
| 52 | #define B0RAT_6 0x00000600 /* Bank 0 Read Access Time = 6 cycles */ |
| 53 | #define B0RAT_7 0x00000700 /* Bank 0 Read Access Time = 7 cycles */ |
| 54 | #define B0RAT_8 0x00000800 /* Bank 0 Read Access Time = 8 cycles */ |
| 55 | #define B0RAT_9 0x00000900 /* Bank 0 Read Access Time = 9 cycles */ |
| 56 | #define B0RAT_10 0x00000A00 /* Bank 0 Read Access Time = 10 cycles */ |
| 57 | #define B0RAT_11 0x00000B00 /* Bank 0 Read Access Time = 11 cycles */ |
| 58 | #define B0RAT_12 0x00000C00 /* Bank 0 Read Access Time = 12 cycles */ |
| 59 | #define B0RAT_13 0x00000D00 /* Bank 0 Read Access Time = 13 cycles */ |
| 60 | #define B0RAT_14 0x00000E00 /* Bank 0 Read Access Time = 14 cycles */ |
| 61 | #define B0RAT_15 0x00000F00 /* Bank 0 Read Access Time = 15 cycles */ |
| 62 | #define B0WAT_1 0x00001000 /* Bank 0 Write Access Time = 1 cycle */ |
| 63 | #define B0WAT_2 0x00002000 /* Bank 0 Write Access Time = 2 cycles */ |
| 64 | #define B0WAT_3 0x00003000 /* Bank 0 Write Access Time = 3 cycles */ |
| 65 | #define B0WAT_4 0x00004000 /* Bank 0 Write Access Time = 4 cycles */ |
| 66 | #define B0WAT_5 0x00005000 /* Bank 0 Write Access Time = 5 cycles */ |
| 67 | #define B0WAT_6 0x00006000 /* Bank 0 Write Access Time = 6 cycles */ |
| 68 | #define B0WAT_7 0x00007000 /* Bank 0 Write Access Time = 7 cycles */ |
| 69 | #define B0WAT_8 0x00008000 /* Bank 0 Write Access Time = 8 cycles */ |
| 70 | #define B0WAT_9 0x00009000 /* Bank 0 Write Access Time = 9 cycles */ |
| 71 | #define B0WAT_10 0x0000A000 /* Bank 0 Write Access Time = 10 cycles */ |
| 72 | #define B0WAT_11 0x0000B000 /* Bank 0 Write Access Time = 11 cycles */ |
| 73 | #define B0WAT_12 0x0000C000 /* Bank 0 Write Access Time = 12 cycles */ |
| 74 | #define B0WAT_13 0x0000D000 /* Bank 0 Write Access Time = 13 cycles */ |
| 75 | #define B0WAT_14 0x0000E000 /* Bank 0 Write Access Time = 14 cycles */ |
| 76 | #define B0WAT_15 0x0000F000 /* Bank 0 Write Access Time = 15 cycles */ |
| 77 | #define B1RDYEN 0x00010000 /* Bank 1 RDY enable, 0=disable, 1=enable */ |
| 78 | #define B1RDYPOL 0x00020000 /* Bank 1 RDY Active high, 0=active low, 1=active high */ |
| 79 | #define B1TT_1 0x00040000 /* Bank 1 Transition Time from Read to Write = 1 cycle */ |
| 80 | #define B1TT_2 0x00080000 /* Bank 1 Transition Time from Read to Write = 2 cycles */ |
| 81 | #define B1TT_3 0x000C0000 /* Bank 1 Transition Time from Read to Write = 3 cycles */ |
| 82 | #define B1TT_4 0x00000000 /* Bank 1 Transition Time from Read to Write = 4 cycles */ |
| 83 | #define B1ST_1 0x00100000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */ |
| 84 | #define B1ST_2 0x00200000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */ |
| 85 | #define B1ST_3 0x00300000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */ |
| 86 | #define B1ST_4 0x00000000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */ |
| 87 | #define B1HT_1 0x00400000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */ |
| 88 | #define B1HT_2 0x00800000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */ |
| 89 | #define B1HT_3 0x00C00000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */ |
| 90 | #define B1HT_0 0x00000000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */ |
| 91 | #define B1RAT_1 0x01000000 /* Bank 1 Read Access Time = 1 cycle */ |
| 92 | #define B1RAT_2 0x02000000 /* Bank 1 Read Access Time = 2 cycles */ |
| 93 | #define B1RAT_3 0x03000000 /* Bank 1 Read Access Time = 3 cycles */ |
| 94 | #define B1RAT_4 0x04000000 /* Bank 1 Read Access Time = 4 cycles */ |
| 95 | #define B1RAT_5 0x05000000 /* Bank 1 Read Access Time = 5 cycles */ |
| 96 | #define B1RAT_6 0x06000000 /* Bank 1 Read Access Time = 6 cycles */ |
| 97 | #define B1RAT_7 0x07000000 /* Bank 1 Read Access Time = 7 cycles */ |
| 98 | #define B1RAT_8 0x08000000 /* Bank 1 Read Access Time = 8 cycles */ |
| 99 | #define B1RAT_9 0x09000000 /* Bank 1 Read Access Time = 9 cycles */ |
| 100 | #define B1RAT_10 0x0A000000 /* Bank 1 Read Access Time = 10 cycles */ |
| 101 | #define B1RAT_11 0x0B000000 /* Bank 1 Read Access Time = 11 cycles */ |
| 102 | #define B1RAT_12 0x0C000000 /* Bank 1 Read Access Time = 12 cycles */ |
| 103 | #define B1RAT_13 0x0D000000 /* Bank 1 Read Access Time = 13 cycles */ |
| 104 | #define B1RAT_14 0x0E000000 /* Bank 1 Read Access Time = 14 cycles */ |
| 105 | #define B1RAT_15 0x0F000000 /* Bank 1 Read Access Time = 15 cycles */ |
| 106 | #define B1WAT_1 0x10000000 /* Bank 1 Write Access Time = 1 cycle */ |
| 107 | #define B1WAT_2 0x20000000 /* Bank 1 Write Access Time = 2 cycles */ |
| 108 | #define B1WAT_3 0x30000000 /* Bank 1 Write Access Time = 3 cycles */ |
| 109 | #define B1WAT_4 0x40000000 /* Bank 1 Write Access Time = 4 cycles */ |
| 110 | #define B1WAT_5 0x50000000 /* Bank 1 Write Access Time = 5 cycles */ |
| 111 | #define B1WAT_6 0x60000000 /* Bank 1 Write Access Time = 6 cycles */ |
| 112 | #define B1WAT_7 0x70000000 /* Bank 1 Write Access Time = 7 cycles */ |
| 113 | #define B1WAT_8 0x80000000 /* Bank 1 Write Access Time = 8 cycles */ |
| 114 | #define B1WAT_9 0x90000000 /* Bank 1 Write Access Time = 9 cycles */ |
| 115 | #define B1WAT_10 0xA0000000 /* Bank 1 Write Access Time = 10 cycles */ |
| 116 | #define B1WAT_11 0xB0000000 /* Bank 1 Write Access Time = 11 cycles */ |
| 117 | #define B1WAT_12 0xC0000000 /* Bank 1 Write Access Time = 12 cycles */ |
| 118 | #define B1WAT_13 0xD0000000 /* Bank 1 Write Access Time = 13 cycles */ |
| 119 | #define B1WAT_14 0xE0000000 /* Bank 1 Write Access Time = 14 cycles */ |
| 120 | #define B1WAT_15 0xF0000000 /* Bank 1 Write Access Time = 15 cycles */ |
| 121 | |
| 122 | /* EBIU_AMBCTL1 Masks */ |
| 123 | #define B2RDYEN 0x00000001 /* Bank 2 RDY Enable, 0=disable, 1=enable */ |
| 124 | #define B2RDYPOL 0x00000002 /* Bank 2 RDY Active high, 0=active low, 1=active high */ |
| 125 | #define B2TT_1 0x00000004 /* Bank 2 Transition Time from Read to Write = 1 cycle */ |
| 126 | #define B2TT_2 0x00000008 /* Bank 2 Transition Time from Read to Write = 2 cycles */ |
| 127 | #define B2TT_3 0x0000000C /* Bank 2 Transition Time from Read to Write = 3 cycles */ |
| 128 | #define B2TT_4 0x00000000 /* Bank 2 Transition Time from Read to Write = 4 cycles */ |
| 129 | #define B2ST_1 0x00000010 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */ |
| 130 | #define B2ST_2 0x00000020 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */ |
| 131 | #define B2ST_3 0x00000030 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */ |
| 132 | #define B2ST_4 0x00000000 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */ |
| 133 | #define B2HT_1 0x00000040 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */ |
| 134 | #define B2HT_2 0x00000080 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */ |
| 135 | #define B2HT_3 0x000000C0 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */ |
| 136 | #define B2HT_0 0x00000000 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */ |
| 137 | #define B2RAT_1 0x00000100 /* Bank 2 Read Access Time = 1 cycle */ |
| 138 | #define B2RAT_2 0x00000200 /* Bank 2 Read Access Time = 2 cycles */ |
| 139 | #define B2RAT_3 0x00000300 /* Bank 2 Read Access Time = 3 cycles */ |
| 140 | #define B2RAT_4 0x00000400 /* Bank 2 Read Access Time = 4 cycles */ |
| 141 | #define B2RAT_5 0x00000500 /* Bank 2 Read Access Time = 5 cycles */ |
| 142 | #define B2RAT_6 0x00000600 /* Bank 2 Read Access Time = 6 cycles */ |
| 143 | #define B2RAT_7 0x00000700 /* Bank 2 Read Access Time = 7 cycles */ |
| 144 | #define B2RAT_8 0x00000800 /* Bank 2 Read Access Time = 8 cycles */ |
| 145 | #define B2RAT_9 0x00000900 /* Bank 2 Read Access Time = 9 cycles */ |
| 146 | #define B2RAT_10 0x00000A00 /* Bank 2 Read Access Time = 10 cycles */ |
| 147 | #define B2RAT_11 0x00000B00 /* Bank 2 Read Access Time = 11 cycles */ |
| 148 | #define B2RAT_12 0x00000C00 /* Bank 2 Read Access Time = 12 cycles */ |
| 149 | #define B2RAT_13 0x00000D00 /* Bank 2 Read Access Time = 13 cycles */ |
| 150 | #define B2RAT_14 0x00000E00 /* Bank 2 Read Access Time = 14 cycles */ |
| 151 | #define B2RAT_15 0x00000F00 /* Bank 2 Read Access Time = 15 cycles */ |
| 152 | #define B2WAT_1 0x00001000 /* Bank 2 Write Access Time = 1 cycle */ |
| 153 | #define B2WAT_2 0x00002000 /* Bank 2 Write Access Time = 2 cycles */ |
| 154 | #define B2WAT_3 0x00003000 /* Bank 2 Write Access Time = 3 cycles */ |
| 155 | #define B2WAT_4 0x00004000 /* Bank 2 Write Access Time = 4 cycles */ |
| 156 | #define B2WAT_5 0x00005000 /* Bank 2 Write Access Time = 5 cycles */ |
| 157 | #define B2WAT_6 0x00006000 /* Bank 2 Write Access Time = 6 cycles */ |
| 158 | #define B2WAT_7 0x00007000 /* Bank 2 Write Access Time = 7 cycles */ |
| 159 | #define B2WAT_8 0x00008000 /* Bank 2 Write Access Time = 8 cycles */ |
| 160 | #define B2WAT_9 0x00009000 /* Bank 2 Write Access Time = 9 cycles */ |
| 161 | #define B2WAT_10 0x0000A000 /* Bank 2 Write Access Time = 10 cycles */ |
| 162 | #define B2WAT_11 0x0000B000 /* Bank 2 Write Access Time = 11 cycles */ |
| 163 | #define B2WAT_12 0x0000C000 /* Bank 2 Write Access Time = 12 cycles */ |
| 164 | #define B2WAT_13 0x0000D000 /* Bank 2 Write Access Time = 13 cycles */ |
| 165 | #define B2WAT_14 0x0000E000 /* Bank 2 Write Access Time = 14 cycles */ |
| 166 | #define B2WAT_15 0x0000F000 /* Bank 2 Write Access Time = 15 cycles */ |
| 167 | #define B3RDYEN 0x00010000 /* Bank 3 RDY enable, 0=disable, 1=enable */ |
| 168 | #define B3RDYPOL 0x00020000 /* Bank 3 RDY Active high, 0=active low, 1=active high */ |
| 169 | #define B3TT_1 0x00040000 /* Bank 3 Transition Time from Read to Write = 1 cycle */ |
| 170 | #define B3TT_2 0x00080000 /* Bank 3 Transition Time from Read to Write = 2 cycles */ |
| 171 | #define B3TT_3 0x000C0000 /* Bank 3 Transition Time from Read to Write = 3 cycles */ |
| 172 | #define B3TT_4 0x00000000 /* Bank 3 Transition Time from Read to Write = 4 cycles */ |
| 173 | #define B3ST_1 0x00100000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */ |
| 174 | #define B3ST_2 0x00200000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */ |
| 175 | #define B3ST_3 0x00300000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */ |
| 176 | #define B3ST_4 0x00000000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */ |
| 177 | #define B3HT_1 0x00400000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */ |
| 178 | #define B3HT_2 0x00800000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */ |
| 179 | #define B3HT_3 0x00C00000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */ |
| 180 | #define B3HT_0 0x00000000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */ |
| 181 | #define B3RAT_1 0x01000000 /* Bank 3 Read Access Time = 1 cycle */ |
| 182 | #define B3RAT_2 0x02000000 /* Bank 3 Read Access Time = 2 cycles */ |
| 183 | #define B3RAT_3 0x03000000 /* Bank 3 Read Access Time = 3 cycles */ |
| 184 | #define B3RAT_4 0x04000000 /* Bank 3 Read Access Time = 4 cycles */ |
| 185 | #define B3RAT_5 0x05000000 /* Bank 3 Read Access Time = 5 cycles */ |
| 186 | #define B3RAT_6 0x06000000 /* Bank 3 Read Access Time = 6 cycles */ |
| 187 | #define B3RAT_7 0x07000000 /* Bank 3 Read Access Time = 7 cycles */ |
| 188 | #define B3RAT_8 0x08000000 /* Bank 3 Read Access Time = 8 cycles */ |
| 189 | #define B3RAT_9 0x09000000 /* Bank 3 Read Access Time = 9 cycles */ |
| 190 | #define B3RAT_10 0x0A000000 /* Bank 3 Read Access Time = 10 cycles */ |
| 191 | #define B3RAT_11 0x0B000000 /* Bank 3 Read Access Time = 11 cycles */ |
| 192 | #define B3RAT_12 0x0C000000 /* Bank 3 Read Access Time = 12 cycles */ |
| 193 | #define B3RAT_13 0x0D000000 /* Bank 3 Read Access Time = 13 cycles */ |
| 194 | #define B3RAT_14 0x0E000000 /* Bank 3 Read Access Time = 14 cycles */ |
| 195 | #define B3RAT_15 0x0F000000 /* Bank 3 Read Access Time = 15 cycles */ |
| 196 | #define B3WAT_1 0x10000000 /* Bank 3 Write Access Time = 1 cycle */ |
| 197 | #define B3WAT_2 0x20000000 /* Bank 3 Write Access Time = 2 cycles */ |
| 198 | #define B3WAT_3 0x30000000 /* Bank 3 Write Access Time = 3 cycles */ |
| 199 | #define B3WAT_4 0x40000000 /* Bank 3 Write Access Time = 4 cycles */ |
| 200 | #define B3WAT_5 0x50000000 /* Bank 3 Write Access Time = 5 cycles */ |
| 201 | #define B3WAT_6 0x60000000 /* Bank 3 Write Access Time = 6 cycles */ |
| 202 | #define B3WAT_7 0x70000000 /* Bank 3 Write Access Time = 7 cycles */ |
| 203 | #define B3WAT_8 0x80000000 /* Bank 3 Write Access Time = 8 cycles */ |
| 204 | #define B3WAT_9 0x90000000 /* Bank 3 Write Access Time = 9 cycles */ |
| 205 | #define B3WAT_10 0xA0000000 /* Bank 3 Write Access Time = 10 cycles */ |
| 206 | #define B3WAT_11 0xB0000000 /* Bank 3 Write Access Time = 11 cycles */ |
| 207 | #define B3WAT_12 0xC0000000 /* Bank 3 Write Access Time = 12 cycles */ |
| 208 | #define B3WAT_13 0xD0000000 /* Bank 3 Write Access Time = 13 cycles */ |
| 209 | #define B3WAT_14 0xE0000000 /* Bank 3 Write Access Time = 14 cycles */ |
| 210 | #define B3WAT_15 0xF0000000 /* Bank 3 Write Access Time = 15 cycles */ |
| 211 | |
| 212 | /* Only available on newer parts */ |
| 213 | #ifdef EBIU_MODE |
| 214 | |
| 215 | /* EBIU_MBSCTL Bit Positions */ |
| 216 | #define AMSB0CTL_P 0 |
| 217 | #define AMSB1CTL_P 2 |
| 218 | #define AMSB2CTL_P 4 |
| 219 | #define AMSB3CTL_P 6 |
| 220 | |
| 221 | /* EBIU_MBSCTL Masks */ |
| 222 | #define AMSB0CTL_MASK (0x3 << AMSB0CTL_P) /* Async Memory Bank 0 Control Modes */ |
| 223 | #define AMSB0CTL_NONE (0x0 << AMSB0CTL_P) /* Control Mode - 00 - No logic */ |
| 224 | #define AMSB0CTL_ARE (0x1 << AMSB0CTL_P) /* Control Mode - 01 - OR-ed with /ARE */ |
| 225 | #define AMSB0CTL_AOE (0x2 << AMSB0CTL_P) /* Control Mode - 02 - OR-ed with /AOE */ |
| 226 | #define AMSB0CTL_AWE (0x3 << AMSB0CTL_P) /* Control Mode - 03 - OR-ed with /AWE */ |
| 227 | #define AMSB1CTL_MASK (0x3 << AMSB1CTL_P) /* Async Memory Bank 1 Control Modes */ |
| 228 | #define AMSB1CTL_NONE (0x0 << AMSB1CTL_P) /* Control Mode - 00 - No logic */ |
| 229 | #define AMSB1CTL_ARE (0x1 << AMSB1CTL_P) /* Control Mode - 01 - OR-ed with /ARE */ |
| 230 | #define AMSB1CTL_AOE (0x2 << AMSB1CTL_P) /* Control Mode - 02 - OR-ed with /AOE */ |
| 231 | #define AMSB1CTL_AWE (0x3 << AMSB1CTL_P) /* Control Mode - 03 - OR-ed with /AWE */ |
| 232 | #define AMSB2CTL_MASK (0x3 << AMSB2CTL_P) /* Async Memory Bank 2 Control Modes */ |
| 233 | #define AMSB2CTL_NONE (0x0 << AMSB2CTL_P) /* Control Mode - 00 - No logic */ |
| 234 | #define AMSB2CTL_ARE (0x1 << AMSB2CTL_P) /* Control Mode - 01 - OR-ed with /ARE */ |
| 235 | #define AMSB2CTL_AOE (0x2 << AMSB2CTL_P) /* Control Mode - 02 - OR-ed with /AOE */ |
| 236 | #define AMSB2CTL_AWE (0x3 << AMSB2CTL_P) /* Control Mode - 03 - OR-ed with /AWE */ |
| 237 | #define AMSB3CTL_MASK (0x3 << AMSB3CTL_P) /* Async Memory Bank 3 Control Modes */ |
| 238 | #define AMSB3CTL_NONE (0x0 << AMSB3CTL_P) /* Control Mode - 00 - No logic */ |
| 239 | #define AMSB3CTL_ARE (0x1 << AMSB3CTL_P) /* Control Mode - 01 - OR-ed with /ARE */ |
| 240 | #define AMSB3CTL_AOE (0x2 << AMSB3CTL_P) /* Control Mode - 02 - OR-ed with /AOE */ |
| 241 | #define AMSB3CTL_AWE (0x3 << AMSB3CTL_P) /* Control Mode - 03 - OR-ed with /AWE */ |
| 242 | |
| 243 | /* EBIU_MODE Bit Positions */ |
| 244 | #define B0MODE_P 0 |
| 245 | #define B1MODE_P 2 |
| 246 | #define B2MODE_P 4 |
| 247 | #define B3MODE_P 6 |
| 248 | |
| 249 | /* EBIU_MODE Masks */ |
| 250 | #define B0MODE_MASK (0x3 << B0MODE_P) /* Async Memory Bank 0 Access Mode */ |
| 251 | #define B0MODE_ASYNC (0x0 << B0MODE_P) /* Access Mode - 00 - Asynchronous Mode */ |
| 252 | #define B0MODE_FLASH (0x1 << B0MODE_P) /* Access Mode - 01 - Asynchronous Flash Mode */ |
| 253 | #define B0MODE_PAGE (0x2 << B0MODE_P) /* Access Mode - 10 - Asynchronous Page Mode */ |
| 254 | #define B0MODE_BURST (0x3 << B0MODE_P) /* Access Mode - 11 - Synchronous (Burst) Mode */ |
| 255 | #define B1MODE_MASK (0x3 << B1MODE_P) /* Async Memory Bank 1 Access Mode */ |
| 256 | #define B1MODE_ASYNC (0x0 << B1MODE_P) /* Access Mode - 00 - Asynchronous Mode */ |
| 257 | #define B1MODE_FLASH (0x1 << B1MODE_P) /* Access Mode - 01 - Asynchronous Flash Mode */ |
| 258 | #define B1MODE_PAGE (0x2 << B1MODE_P) /* Access Mode - 10 - Asynchronous Page Mode */ |
| 259 | #define B1MODE_BURST (0x3 << B1MODE_P) /* Access Mode - 11 - Synchronous (Burst) Mode */ |
| 260 | #define B2MODE_MASK (0x3 << B2MODE_P) /* Async Memory Bank 2 Access Mode */ |
| 261 | #define B2MODE_ASYNC (0x0 << B2MODE_P) /* Access Mode - 00 - Asynchronous Mode */ |
| 262 | #define B2MODE_FLASH (0x1 << B2MODE_P) /* Access Mode - 01 - Asynchronous Flash Mode */ |
| 263 | #define B2MODE_PAGE (0x2 << B2MODE_P) /* Access Mode - 10 - Asynchronous Page Mode */ |
| 264 | #define B2MODE_BURST (0x3 << B2MODE_P) /* Access Mode - 11 - Synchronous (Burst) Mode */ |
| 265 | #define B3MODE_MASK (0x3 << B3MODE_P) /* Async Memory Bank 3 Access Mode */ |
| 266 | #define B3MODE_ASYNC (0x0 << B3MODE_P) /* Access Mode - 00 - Asynchronous Mode */ |
| 267 | #define B3MODE_FLASH (0x1 << B3MODE_P) /* Access Mode - 01 - Asynchronous Flash Mode */ |
| 268 | #define B3MODE_PAGE (0x2 << B3MODE_P) /* Access Mode - 10 - Asynchronous Page Mode */ |
| 269 | #define B3MODE_BURST (0x3 << B3MODE_P) /* Access Mode - 11 - Synchronous (Burst) Mode */ |
| 270 | |
| 271 | /* EBIU_FCTL Bit Positions */ |
| 272 | #define TESTSETLOCK_P 0 |
| 273 | #define BCLK_P 1 |
| 274 | #define PGWS_P 3 |
| 275 | #define PGSZ_P 6 |
| 276 | #define RDDL_P 7 |
| 277 | |
| 278 | /* EBIU_FCTL Masks */ |
| 279 | #define TESTSETLOCK (0x1 << TESTSETLOCK_P) /* Test set lock */ |
| 280 | #define BCLK_MASK (0x3 << BCLK_P) /* Burst clock frequency */ |
| 281 | #define BCLK_2 (0x1 << BCLK_P) /* Burst clock frequency - SCLK/2 */ |
| 282 | #define BCLK_3 (0x2 << BCLK_P) /* Burst clock frequency - SCLK/3 */ |
| 283 | #define BCLK_4 (0x3 << BCLK_P) /* Burst clock frequency - SCLK/4 */ |
| 284 | #define PGWS_MASK (0x7 << PGWS_P) /* Page wait states */ |
| 285 | #define PGWS_0 (0x0 << PGWS_P) /* Page wait states - 0 cycles */ |
| 286 | #define PGWS_1 (0x1 << PGWS_P) /* Page wait states - 1 cycles */ |
| 287 | #define PGWS_2 (0x2 << PGWS_P) /* Page wait states - 2 cycles */ |
| 288 | #define PGWS_3 (0x3 << PGWS_P) /* Page wait states - 3 cycles */ |
| 289 | #define PGWS_4 (0x4 << PGWS_P) /* Page wait states - 4 cycles */ |
| 290 | #define PGSZ (0x1 << PGSZ_P) /* Page size */ |
| 291 | #define PGSZ_4 (0x0 << PGSZ_P) /* Page size - 4 words */ |
| 292 | #define PGSZ_8 (0x1 << PGSZ_P) /* Page size - 8 words */ |
| 293 | #define RDDL (0x38 << RDDL_P) /* Read data delay */ |
| 294 | |
| 295 | /* EBIU_ARBSTAT Masks */ |
| 296 | #define ARBSTAT 0x00000001 /* Arbitration status */ |
| 297 | #define BGSTAT 0x00000002 /* External Bus grant status */ |
| 298 | |
| 299 | #endif /* EBIU_MODE */ |
| 300 | |
| 301 | /* Only available on SDRAM based-parts */ |
| 302 | #ifdef EBIU_SDGCTL |
| 303 | |
| 304 | /* EBIU_SDGCTL Masks */ |
| 305 | #define SCTLE 0x00000001 /* Enable SCLK[0], /SRAS, /SCAS, /SWE, SDQM[3:0] */ |
| 306 | #define SCK1E 0x00000002 /* Enable CLKOUT, /SCLK1 */ |
| 307 | #define CL_2 0x00000008 /* SDRAM CAS latency = 2 cycles */ |
| 308 | #define CL_3 0x0000000C /* SDRAM CAS latency = 3 cycles */ |
| 309 | #define PASR_ALL 0x00000000 /* All 4 SDRAM Banks Refreshed In Self-Refresh */ |
| 310 | #define PASR_B0_B1 0x00000010 /* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh */ |
| 311 | #define PASR_B0 0x00000020 /* Only SDRAM Bank 0 Is Refreshed In Self-Refresh */ |
| 312 | #define TRAS_1 0x00000040 /* SDRAM tRAS = 1 cycle */ |
| 313 | #define TRAS_2 0x00000080 /* SDRAM tRAS = 2 cycles */ |
| 314 | #define TRAS_3 0x000000C0 /* SDRAM tRAS = 3 cycles */ |
| 315 | #define TRAS_4 0x00000100 /* SDRAM tRAS = 4 cycles */ |
| 316 | #define TRAS_5 0x00000140 /* SDRAM tRAS = 5 cycles */ |
| 317 | #define TRAS_6 0x00000180 /* SDRAM tRAS = 6 cycles */ |
| 318 | #define TRAS_7 0x000001C0 /* SDRAM tRAS = 7 cycles */ |
| 319 | #define TRAS_8 0x00000200 /* SDRAM tRAS = 8 cycles */ |
| 320 | #define TRAS_9 0x00000240 /* SDRAM tRAS = 9 cycles */ |
| 321 | #define TRAS_10 0x00000280 /* SDRAM tRAS = 10 cycles */ |
| 322 | #define TRAS_11 0x000002C0 /* SDRAM tRAS = 11 cycles */ |
| 323 | #define TRAS_12 0x00000300 /* SDRAM tRAS = 12 cycles */ |
| 324 | #define TRAS_13 0x00000340 /* SDRAM tRAS = 13 cycles */ |
| 325 | #define TRAS_14 0x00000380 /* SDRAM tRAS = 14 cycles */ |
| 326 | #define TRAS_15 0x000003C0 /* SDRAM tRAS = 15 cycles */ |
| 327 | #define TRP_1 0x00000800 /* SDRAM tRP = 1 cycle */ |
| 328 | #define TRP_2 0x00001000 /* SDRAM tRP = 2 cycles */ |
| 329 | #define TRP_3 0x00001800 /* SDRAM tRP = 3 cycles */ |
| 330 | #define TRP_4 0x00002000 /* SDRAM tRP = 4 cycles */ |
| 331 | #define TRP_5 0x00002800 /* SDRAM tRP = 5 cycles */ |
| 332 | #define TRP_6 0x00003000 /* SDRAM tRP = 6 cycles */ |
| 333 | #define TRP_7 0x00003800 /* SDRAM tRP = 7 cycles */ |
| 334 | #define TRCD_1 0x00008000 /* SDRAM tRCD = 1 cycle */ |
| 335 | #define TRCD_2 0x00010000 /* SDRAM tRCD = 2 cycles */ |
| 336 | #define TRCD_3 0x00018000 /* SDRAM tRCD = 3 cycles */ |
| 337 | #define TRCD_4 0x00020000 /* SDRAM tRCD = 4 cycles */ |
| 338 | #define TRCD_5 0x00028000 /* SDRAM tRCD = 5 cycles */ |
| 339 | #define TRCD_6 0x00030000 /* SDRAM tRCD = 6 cycles */ |
| 340 | #define TRCD_7 0x00038000 /* SDRAM tRCD = 7 cycles */ |
| 341 | #define TWR_1 0x00080000 /* SDRAM tWR = 1 cycle */ |
| 342 | #define TWR_2 0x00100000 /* SDRAM tWR = 2 cycles */ |
| 343 | #define TWR_3 0x00180000 /* SDRAM tWR = 3 cycles */ |
| 344 | #define PUPSD 0x00200000 /* Power-up start delay */ |
| 345 | #define PSM 0x00400000 /* SDRAM power-up sequence = Precharge, mode register set, 8 CBR refresh cycles */ |
| 346 | #define PSS 0x00800000 /* enable SDRAM power-up sequence on next SDRAM access */ |
| 347 | #define SRFS 0x01000000 /* Start SDRAM self-refresh mode */ |
| 348 | #define EBUFE 0x02000000 /* Enable external buffering timing */ |
| 349 | #define FBBRW 0x04000000 /* Fast back-to-back read write enable */ |
| 350 | #define EMREN 0x10000000 /* Extended mode register enable */ |
| 351 | #define TCSR 0x20000000 /* Temp compensated self refresh value 85 deg C */ |
| 352 | #define CDDBG 0x40000000 /* Tristate SDRAM controls during bus grant */ |
| 353 | |
| 354 | /* EBIU_SDBCTL Masks */ |
| 355 | #define EBE 0x0001 /* Enable SDRAM External Bank */ |
| 356 | #define EBSZ_16 0x0000 /* SDRAM External Bank Size = 16MB */ |
| 357 | #define EBSZ_32 0x0002 /* SDRAM External Bank Size = 32MB */ |
| 358 | #define EBSZ_64 0x0004 /* SDRAM External Bank Size = 64MB */ |
| 359 | #define EBSZ_128 0x0006 /* SDRAM External Bank Size = 128MB */ |
| Mike Frysinger | 4093728 | 2008-11-11 05:43:57 -0500 | [diff] [blame] | 360 | #define EBSZ_256 0x0008 /* SDRAM External Bank Size = 256MB */ |
| 361 | #define EBSZ_512 0x000A /* SDRAM External Bank Size = 512MB */ |
| Mike Frysinger | 66c4cf4 | 2008-02-04 19:26:55 -0500 | [diff] [blame] | 362 | #define EBCAW_8 0x0000 /* SDRAM External Bank Column Address Width = 8 Bits */ |
| 363 | #define EBCAW_9 0x0010 /* SDRAM External Bank Column Address Width = 9 Bits */ |
| 364 | #define EBCAW_10 0x0020 /* SDRAM External Bank Column Address Width = 10 Bits */ |
| 365 | #define EBCAW_11 0x0030 /* SDRAM External Bank Column Address Width = 11 Bits */ |
| 366 | |
| 367 | #ifdef __ADSPBF561__ |
| 368 | |
| 369 | #define EB0E (EBE<<0) /* Enable SDRAM external bank 0 */ |
| 370 | #define EB0SZ_16 (EBSZ_16<<0) /* SDRAM external bank size = 16MB */ |
| 371 | #define EB0SZ_32 (EBSZ_32<<0) /* SDRAM external bank size = 32MB */ |
| 372 | #define EB0SZ_64 (EBSZ_64<<0) /* SDRAM external bank size = 64MB */ |
| 373 | #define EB0SZ_128 (EBSZ_128<<0) /* SDRAM external bank size = 128MB */ |
| 374 | #define EB0CAW_8 (EBCAW_8<<0) /* SDRAM external bank column address width = 8 bits */ |
| 375 | #define EB0CAW_9 (EBCAW_9<<0) /* SDRAM external bank column address width = 9 bits */ |
| 376 | #define EB0CAW_10 (EBCAW_10<<0) /* SDRAM external bank column address width = 9 bits */ |
| 377 | #define EB0CAW_11 (EBCAW_11<<0) /* SDRAM external bank column address width = 9 bits */ |
| 378 | |
| 379 | #define EB1E (EBE<<8) /* Enable SDRAM external bank 0 */ |
| 380 | #define EB1SZ_16 (EBSZ_16<<8) /* SDRAM external bank size = 16MB */ |
| 381 | #define EB1SZ_32 (EBSZ_32<<8) /* SDRAM external bank size = 32MB */ |
| 382 | #define EB1SZ_64 (EBSZ_64<<8) /* SDRAM external bank size = 64MB */ |
| 383 | #define EB1SZ_128 (EBSZ_128<<8) /* SDRAM external bank size = 128MB */ |
| 384 | #define EB1CAW_8 (EBCAW_8<<8) /* SDRAM external bank column address width = 8 bits */ |
| 385 | #define EB1CAW_9 (EBCAW_9<<8) /* SDRAM external bank column address width = 9 bits */ |
| 386 | #define EB1CAW_10 (EBCAW_10<<8) /* SDRAM external bank column address width = 9 bits */ |
| 387 | #define EB1CAW_11 (EBCAW_11<<8) /* SDRAM external bank column address width = 9 bits */ |
| 388 | |
| 389 | #define EB2E (EBE<<16) /* Enable SDRAM external bank 0 */ |
| 390 | #define EB2SZ_16 (EBSZ_16<<16) /* SDRAM external bank size = 16MB */ |
| 391 | #define EB2SZ_32 (EBSZ_32<<16) /* SDRAM external bank size = 32MB */ |
| 392 | #define EB2SZ_64 (EBSZ_64<<16) /* SDRAM external bank size = 64MB */ |
| 393 | #define EB2SZ_128 (EBSZ_128<<16) /* SDRAM external bank size = 128MB */ |
| 394 | #define EB2CAW_8 (EBCAW_8<<16) /* SDRAM external bank column address width = 8 bits */ |
| 395 | #define EB2CAW_9 (EBCAW_9<<16) /* SDRAM external bank column address width = 9 bits */ |
| 396 | #define EB2CAW_10 (EBCAW_10<<16) /* SDRAM external bank column address width = 9 bits */ |
| 397 | #define EB2CAW_11 (EBCAW_11<<16) /* SDRAM external bank column address width = 9 bits */ |
| 398 | |
| 399 | #define EB3E (EBE<<24) /* Enable SDRAM external bank 0 */ |
| 400 | #define EB3SZ_16 (EBSZ_16<<24) /* SDRAM external bank size = 16MB */ |
| 401 | #define EB3SZ_32 (EBSZ_32<<24) /* SDRAM external bank size = 32MB */ |
| 402 | #define EB3SZ_64 (EBSZ_64<<24) /* SDRAM external bank size = 64MB */ |
| 403 | #define EB3SZ_128 (EBSZ_128<<24) /* SDRAM external bank size = 128MB */ |
| 404 | #define EB3CAW_8 (EBCAW_8<<24) /* SDRAM external bank column address width = 8 bits */ |
| 405 | #define EB3CAW_9 (EBCAW_9<<24) /* SDRAM external bank column address width = 9 bits */ |
| 406 | #define EB3CAW_10 (EBCAW_10<<24) /* SDRAM external bank column address width = 9 bits */ |
| 407 | #define EB3CAW_11 (EBCAW_11<<24) /* SDRAM external bank column address width = 9 bits */ |
| 408 | |
| 409 | #endif /* BF561 */ |
| 410 | |
| 411 | /* EBIU_SDSTAT Masks */ |
| 412 | #define SDCI 0x0001 /* SDRAM controller is idle */ |
| Mike Frysinger | a2ea4f1 | 2008-08-07 13:21:27 -0400 | [diff] [blame] | 413 | #define SDSRA 0x0002 /* SDRAM self refresh is active */ |
| Mike Frysinger | 66c4cf4 | 2008-02-04 19:26:55 -0500 | [diff] [blame] | 414 | #define SDPUA 0x0004 /* SDRAM power up active */ |
| 415 | #define SDRS 0x0008 /* SDRAM is in reset state */ |
| 416 | #define SDEASE 0x0010 /* SDRAM EAB sticky error status - W1C */ |
| 417 | #define BGSTAT 0x0020 /* Bus granted */ |
| 418 | |
| Mike Frysinger | a2ea4f1 | 2008-08-07 13:21:27 -0400 | [diff] [blame] | 419 | /* Only available on DDR based-parts */ |
| 420 | #else |
| 421 | |
| 422 | /* EBIU_ERRMST Masks */ |
| 423 | #define DEB0_ERROR 0x0001 /* DEB0 access on reserved memory */ |
| 424 | #define DEB1_ERROR 0x0002 /* DEB1 access on reserved memory */ |
| 425 | #define DEB2_ERROR 0x0004 /* DEB2 (USB) access on reserved memory */ |
| 426 | #define CORE_ERROR 0x0008 /* Core access on reserved memory */ |
| 427 | #define DEB0_MERROR 0x0010 /* DEB0 access on reserved memory and DEB0_ERROR is set */ |
| 428 | #define DEB1_MERROR 0x0020 /* DEB1 access on reserved memory and DEB1_ERROR is set */ |
| 429 | #define DEB2_MERROR 0x0040 /* DEB2 access on reserved memory and DEB2_ERROR is set */ |
| 430 | #define CORE_MERROR 0x0080 /* Core access on reserved memory and CORE_ERROR is set */ |
| 431 | |
| 432 | /* EBIU_RSTCTL Masks */ |
| 433 | #define DDR_SRESET 0x0001 /* Reset Control to DDR Controller */ |
| 434 | #define SRREQ 0x0008 /* Self Refresh Request */ |
| 435 | #define SRACK 0x0010 /* Self Refresh Request Acknowledgement */ |
| 436 | #define MDDRENABLE 0x0020 /* Mobile DDR Enable */ |
| 437 | |
| Mike Frysinger | 66c4cf4 | 2008-02-04 19:26:55 -0500 | [diff] [blame] | 438 | #endif /* EBIU_SDGCTL */ |
| 439 | |
| 440 | #endif |