blob: 00c4c547fd91e45cc6e0f036f8421687aa2557ad [file] [log] [blame]
Poonam Aggrwal4baef822009-07-31 12:08:14 +05301/*
2 * Copyright 2008-2009 Freescale Semiconductor, Inc.
3 * Kumar Gala <kumar.gala@freescale.com>
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
Kumar Gala36d6b3f2008-01-17 16:48:33 -060024#include <config.h>
25#include <mpc85xx.h>
26#include <version.h>
27
28#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
29
30#include <ppc_asm.tmpl>
31#include <ppc_defs.h>
32
33#include <asm/cache.h>
34#include <asm/mmu.h>
35
36/* To boot secondary cpus, we need a place for them to start up.
37 * Normally, they start at 0xfffffffc, but that's usually the
38 * firmware, and we don't want to have to run the firmware again.
39 * Instead, the primary cpu will set the BPTR to point here to
40 * this page. We then set up the core, and head to
41 * start_secondary. Note that this means that the code below
42 * must never exceed 1023 instructions (the branch at the end
43 * would then be the 1024th).
44 */
45 .globl __secondary_start_page
46 .align 12
47__secondary_start_page:
48/* First do some preliminary setup */
49 lis r3, HID0_EMCP@h /* enable machine check */
Kumar Gala9f4a6892008-10-23 01:47:38 -050050#ifndef CONFIG_E500MC
Kumar Gala36d6b3f2008-01-17 16:48:33 -060051 ori r3,r3,HID0_TBEN@l /* enable Timebase */
Kumar Gala9f4a6892008-10-23 01:47:38 -050052#endif
Kumar Gala36d6b3f2008-01-17 16:48:33 -060053#ifdef CONFIG_PHYS_64BIT
54 ori r3,r3,HID0_ENMAS7@l /* enable MAS7 updates */
55#endif
56 mtspr SPRN_HID0,r3
57
Kumar Gala9f4a6892008-10-23 01:47:38 -050058#ifndef CONFIG_E500MC
Kumar Gala36d6b3f2008-01-17 16:48:33 -060059 li r3,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */
60 mtspr SPRN_HID1,r3
Kumar Gala9f4a6892008-10-23 01:47:38 -050061#endif
Kumar Gala36d6b3f2008-01-17 16:48:33 -060062
63 /* Enable branch prediction */
64 li r3,0x201
65 mtspr SPRN_BUCSR,r3
66
Kumar Galab937cc52008-09-08 08:51:29 -050067 /* Ensure TB is 0 */
68 li r3,0
69 mttbl r3
70 mttbu r3
71
Kumar Gala36d6b3f2008-01-17 16:48:33 -060072 /* Enable/invalidate the I-Cache */
73 mfspr r0,SPRN_L1CSR1
74 ori r0,r0,(L1CSR1_ICFI|L1CSR1_ICE)
75 mtspr SPRN_L1CSR1,r0
76 isync
77
78 /* Enable/invalidate the D-Cache */
79 mfspr r0,SPRN_L1CSR0
80 ori r0,r0,(L1CSR0_DCFI|L1CSR0_DCE)
81 msync
82 isync
83 mtspr SPRN_L1CSR0,r0
84 isync
85
86#define toreset(x) (x - __secondary_start_page + 0xfffff000)
87
88 /* get our PIR to figure out our table entry */
89 lis r3,toreset(__spin_table)@h
90 ori r3,r3,toreset(__spin_table)@l
91
Kumar Galadeeac572008-03-26 08:34:25 -050092 /* r10 has the base address for the entry */
Kumar Gala36d6b3f2008-01-17 16:48:33 -060093 mfspr r0,SPRN_PIR
Kumar Gala9f4a6892008-10-23 01:47:38 -050094#ifdef CONFIG_E500MC
95 rlwinm r4,r0,27,27,31
96#else
Kumar Gala36d6b3f2008-01-17 16:48:33 -060097 mr r4,r0
Kumar Gala9f4a6892008-10-23 01:47:38 -050098#endif
Kumar Galadeeac572008-03-26 08:34:25 -050099 slwi r8,r4,5
100 add r10,r3,r8
Kumar Gala36d6b3f2008-01-17 16:48:33 -0600101
Kumar Gala8d2817c2009-03-19 02:53:01 -0500102#if defined(CONFIG_E500MC) && defined(CONFIG_SYS_CACHE_STASHING)
103 /* set stash id to (coreID) * 2 + 32 + L1 CT (0) */
104 slwi r8,r4,1
105 addi r8,r8,32
106 mtspr L1CSR2,r8
107#endif
108
Kumar Galae56f2c52009-03-19 09:16:10 -0500109#ifdef CONFIG_BACKSIDE_L2_CACHE
110 /* Enable/invalidate the L2 cache */
111 msync
Dave Liub8bb4112009-10-31 07:59:55 +0800112 lis r2,(L2CSR0_L2FI|L2CSR0_L2LFC)@h
113 ori r2,r2,(L2CSR0_L2FI|L2CSR0_L2LFC)@l
114 mtspr SPRN_L2CSR0,r2
Kumar Galae56f2c52009-03-19 09:16:10 -05001151:
116 mfspr r3,SPRN_L2CSR0
Dave Liub8bb4112009-10-31 07:59:55 +0800117 and. r1,r3,r2
Kumar Galae56f2c52009-03-19 09:16:10 -0500118 bne 1b
119
Kumar Gala8d2817c2009-03-19 02:53:01 -0500120#ifdef CONFIG_SYS_CACHE_STASHING
121 /* set stash id to (coreID) * 2 + 32 + L2 (1) */
122 addi r3,r8,1
123 mtspr SPRN_L2CSR1,r3
124#endif
125
Kumar Galae56f2c52009-03-19 09:16:10 -0500126 lis r3,CONFIG_SYS_INIT_L2CSR0@h
127 ori r3,r3,CONFIG_SYS_INIT_L2CSR0@l
128 mtspr SPRN_L2CSR0,r3
129 isync
Dave Liub8bb4112009-10-31 07:59:55 +08001302:
131 mfspr r3,SPRN_L2CSR0
132 andis. r1,r3,L2CSR0_L2E@h
133 beq 2b
Kumar Galae56f2c52009-03-19 09:16:10 -0500134#endif
135
Kumar Galadeeac572008-03-26 08:34:25 -0500136#define EPAPR_MAGIC (0x45504150)
137#define ENTRY_ADDR_UPPER 0
138#define ENTRY_ADDR_LOWER 4
139#define ENTRY_R3_UPPER 8
140#define ENTRY_R3_LOWER 12
141#define ENTRY_RESV 16
142#define ENTRY_PIR 20
143#define ENTRY_R6_UPPER 24
144#define ENTRY_R6_LOWER 28
145#define ENTRY_SIZE 32
Kumar Gala36d6b3f2008-01-17 16:48:33 -0600146
147 /* setup the entry */
Kumar Galadeeac572008-03-26 08:34:25 -0500148 li r3,0
Kumar Gala36d6b3f2008-01-17 16:48:33 -0600149 li r8,1
Kumar Galadeeac572008-03-26 08:34:25 -0500150 stw r0,ENTRY_PIR(r10)
151 stw r3,ENTRY_ADDR_UPPER(r10)
152 stw r8,ENTRY_ADDR_LOWER(r10)
153 stw r3,ENTRY_R3_UPPER(r10)
154 stw r4,ENTRY_R3_LOWER(r10)
155 stw r3,ENTRY_R6_UPPER(r10)
156 stw r3,ENTRY_R6_LOWER(r10)
157
Peter Tyser7feaacb2009-10-23 15:55:47 -0500158 /* load r13 with the address of the 'bootpg' in SDRAM */
159 lis r13,toreset(__bootpg_addr)@h
160 ori r13,r13,toreset(__bootpg_addr)@l
161 lwz r13,0(r13)
162
Kumar Galadeeac572008-03-26 08:34:25 -0500163 /* setup mapping for AS = 1, and jump there */
164 lis r11,(MAS0_TLBSEL(1)|MAS0_ESEL(1))@h
165 mtspr SPRN_MAS0,r11
166 lis r11,(MAS1_VALID|MAS1_IPROT)@h
167 ori r11,r11,(MAS1_TS|MAS1_TSIZE(BOOKE_PAGESZ_4K))@l
168 mtspr SPRN_MAS1,r11
Kumar Gala4756ffa2009-11-17 20:21:20 -0600169 oris r11,r13,(MAS2_I|MAS2_G)@h
170 ori r11,r13,(MAS2_I|MAS2_G)@l
Kumar Galadeeac572008-03-26 08:34:25 -0500171 mtspr SPRN_MAS2,r11
Peter Tyser7feaacb2009-10-23 15:55:47 -0500172 oris r11,r13,(MAS3_SX|MAS3_SW|MAS3_SR)@h
173 ori r11,r13,(MAS3_SX|MAS3_SW|MAS3_SR)@l
Kumar Galadeeac572008-03-26 08:34:25 -0500174 mtspr SPRN_MAS3,r11
175 tlbwe
176
177 bl 1f
1781: mflr r11
Peter Tyser7feaacb2009-10-23 15:55:47 -0500179 /*
180 * OR in 0xfff to create a mask of the bootpg SDRAM address. We use
181 * this mask to fixup the cpu spin table and the address that we want
182 * to jump to, eg change them from 0xfffffxxx to 0x7ffffxxx if the
183 * bootpg is at 0x7ffff000 in SDRAM.
184 */
185 ori r13,r13,0xfff
186 and r11, r11, r13
187 and r10, r10, r13
188
189 addi r11,r11,(2f-1b)
Kumar Galadeeac572008-03-26 08:34:25 -0500190 mfmsr r13
191 ori r12,r13,MSR_IS|MSR_DS@l
192
193 mtspr SPRN_SRR0,r11
194 mtspr SPRN_SRR1,r12
195 rfi
Kumar Gala36d6b3f2008-01-17 16:48:33 -0600196
197 /* spin waiting for addr */
Kumar Galadeeac572008-03-26 08:34:25 -05001982:
199 lwz r4,ENTRY_ADDR_LOWER(r10)
Kumar Gala36d6b3f2008-01-17 16:48:33 -0600200 andi. r11,r4,1
Kumar Galadeeac572008-03-26 08:34:25 -0500201 bne 2b
Kumar Gala398dcd62008-04-28 02:24:04 -0500202 isync
Kumar Galadeeac572008-03-26 08:34:25 -0500203
Kumar Galac24a9052009-08-14 13:37:54 -0500204 /* setup IVORs to match fixed offsets */
205#include "fixed_ivor.S"
206
Kumar Galadeeac572008-03-26 08:34:25 -0500207 /* get the upper bits of the addr */
208 lwz r11,ENTRY_ADDR_UPPER(r10)
Kumar Gala36d6b3f2008-01-17 16:48:33 -0600209
210 /* setup branch addr */
Kumar Galadeeac572008-03-26 08:34:25 -0500211 mtspr SPRN_SRR0,r4
Kumar Gala36d6b3f2008-01-17 16:48:33 -0600212
213 /* mark the entry as released */
214 li r8,3
Kumar Galadeeac572008-03-26 08:34:25 -0500215 stw r8,ENTRY_ADDR_LOWER(r10)
Kumar Gala36d6b3f2008-01-17 16:48:33 -0600216
217 /* mask by ~64M to setup our tlb we will jump to */
Kumar Galadeeac572008-03-26 08:34:25 -0500218 rlwinm r12,r4,0,0,5
Kumar Gala36d6b3f2008-01-17 16:48:33 -0600219
Kumar Galadeeac572008-03-26 08:34:25 -0500220 /* setup r3, r4, r5, r6, r7, r8, r9 */
221 lwz r3,ENTRY_R3_LOWER(r10)
222 li r4,0
Kumar Gala36d6b3f2008-01-17 16:48:33 -0600223 li r5,0
Kumar Galadeeac572008-03-26 08:34:25 -0500224 lwz r6,ENTRY_R6_LOWER(r10)
225 lis r7,(64*1024*1024)@h
226 li r8,0
227 li r9,0
Kumar Gala36d6b3f2008-01-17 16:48:33 -0600228
229 /* load up the pir */
Kumar Galadeeac572008-03-26 08:34:25 -0500230 lwz r0,ENTRY_PIR(r10)
Kumar Gala36d6b3f2008-01-17 16:48:33 -0600231 mtspr SPRN_PIR,r0
232 mfspr r0,SPRN_PIR
Kumar Galadeeac572008-03-26 08:34:25 -0500233 stw r0,ENTRY_PIR(r10)
Kumar Gala36d6b3f2008-01-17 16:48:33 -0600234
Haiying Wangf4745512008-12-03 10:08:19 -0500235 mtspr IVPR,r12
Kumar Gala36d6b3f2008-01-17 16:48:33 -0600236/*
237 * Coming here, we know the cpu has one TLB mapping in TLB1[0]
238 * which maps 0xfffff000-0xffffffff one-to-one. We set up a
239 * second mapping that maps addr 1:1 for 64M, and then we jump to
240 * addr
241 */
Kumar Galadeeac572008-03-26 08:34:25 -0500242 lis r10,(MAS0_TLBSEL(1)|MAS0_ESEL(0))@h
243 mtspr SPRN_MAS0,r10
244 lis r10,(MAS1_VALID|MAS1_IPROT)@h
245 ori r10,r10,(MAS1_TSIZE(BOOKE_PAGESZ_64M))@l
246 mtspr SPRN_MAS1,r10
Kumar Gala36d6b3f2008-01-17 16:48:33 -0600247 /* WIMGE = 0b00000 for now */
Kumar Galadeeac572008-03-26 08:34:25 -0500248 mtspr SPRN_MAS2,r12
249 ori r12,r12,(MAS3_SX|MAS3_SW|MAS3_SR)
250 mtspr SPRN_MAS3,r12
251#ifdef CONFIG_ENABLE_36BIT_PHYS
252 mtspr SPRN_MAS7,r11
253#endif
Kumar Gala36d6b3f2008-01-17 16:48:33 -0600254 tlbwe
255
256/* Now we have another mapping for this page, so we jump to that
257 * mapping
258 */
Kumar Galadeeac572008-03-26 08:34:25 -0500259 mtspr SPRN_SRR1,r13
260 rfi
Kumar Gala36d6b3f2008-01-17 16:48:33 -0600261
Peter Tyser7feaacb2009-10-23 15:55:47 -0500262 /*
263 * Allocate some space for the SDRAM address of the bootpg.
264 * This variable has to be in the boot page so that it can
265 * be accessed by secondary cores when they come out of reset.
266 */
267 .globl __bootpg_addr
268__bootpg_addr:
269 .long 0
270
Kumar Gala398dcd62008-04-28 02:24:04 -0500271 .align L1_CACHE_SHIFT
Kumar Gala36d6b3f2008-01-17 16:48:33 -0600272 .globl __spin_table
273__spin_table:
Poonam Aggrwal4baef822009-07-31 12:08:14 +0530274 .space CONFIG_MAX_CPUS*ENTRY_SIZE
Kumar Gala36d6b3f2008-01-17 16:48:33 -0600275
276 /* Fill in the empty space. The actual reset vector is
277 * the last word of the page */
278__secondary_start_code_end:
279 .space 4092 - (__secondary_start_code_end - __secondary_start_page)
280__secondary_reset_vector:
281 b __secondary_start_page