blob: 8f6b16b93bff6f85ed718aa18620936dacdc5cbb [file] [log] [blame]
Andre Schwarz2a293292008-07-09 18:30:44 +02001/*
2 * (C) Copyright 2003-2004
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * (C) Copyright 2004-2008
6 * Matrix-Vision GmbH, andre.schwarz@matrix-vision.de
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27#ifndef __CONFIG_H
28#define __CONFIG_H
29
30#include <version.h>
31
32#define CONFIG_MPC5xxx 1
33#define CONFIG_MPC5200 1
34
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020035#define CONFIG_SYS_MPC5XXX_CLKIN 33000000
Andre Schwarz2a293292008-07-09 18:30:44 +020036
37#define BOOTFLAG_COLD 0x01
38#define BOOTFLAG_WARM 0x02
39
40#define CONFIG_MISC_INIT_R 1
41
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020042#define CONFIG_SYS_CACHELINE_SIZE 32
Wolfgang Denkec1067c2008-08-12 14:54:04 +020043#ifdef CONFIG_CMD_KGDB
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020044#define CONFIG_SYS_CACHELINE_SHIFT 5
Andre Schwarz2a293292008-07-09 18:30:44 +020045#endif
46
47#define CONFIG_PSC_CONSOLE 1
48#define CONFIG_BAUDRATE 115200
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020049#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200, 230400}
Andre Schwarz2a293292008-07-09 18:30:44 +020050
51#define CONFIG_PCI 1
52#define CONFIG_PCI_PNP 1
53#undef CONFIG_PCI_SCAN_SHOW
54#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
55
56#define CONFIG_PCI_MEM_BUS 0x40000000
57#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
58#define CONFIG_PCI_MEM_SIZE 0x10000000
59
60#define CONFIG_PCI_IO_BUS 0x50000000
61#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
62#define CONFIG_PCI_IO_SIZE 0x01000000
63
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020064#define CONFIG_SYS_XLB_PIPELINING 1
Andre Schwarz2a293292008-07-09 18:30:44 +020065#define CONFIG_HIGH_BATS 1
66
67#define MV_CI mvBlueCOUGAR-P
68#define MV_VCI mvBlueCOUGAR-P
69#define MV_FPGA_DATA 0xff860000
André Schwarza8e1d952009-08-27 14:48:35 +020070#define MV_FPGA_SIZE 0
André Schwarz901f5982009-07-17 14:50:24 +020071#define MV_KERNEL_ADDR 0xffd00000
Andre Schwarz2a293292008-07-09 18:30:44 +020072#define MV_INITRD_ADDR 0xff900000
André Schwarz901f5982009-07-17 14:50:24 +020073#define MV_INITRD_LENGTH 0x00400000
Andre Schwarz2a293292008-07-09 18:30:44 +020074#define MV_SCRATCH_ADDR 0x00000000
75#define MV_SCRATCH_LENGTH MV_INITRD_LENGTH
Peter Tyserd78876c2009-09-16 21:38:10 -050076#define MV_SCRIPT_ADDR 0xff840000
77#define MV_SCRIPT_ADDR2 0xff850000
Andre Schwarz2a293292008-07-09 18:30:44 +020078#define MV_DTB_ADDR 0xfffc0000
79
80#define CONFIG_SHOW_BOOT_PROGRESS 1
81
82#define MV_KERNEL_ADDR_RAM 0x00100000
83#define MV_DTB_ADDR_RAM 0x00600000
84#define MV_INITRD_ADDR_RAM 0x01000000
85
86/* pass open firmware flat tree */
87#define CONFIG_OF_LIBFDT 1
88#define CONFIG_OF_BOARD_SETUP 1
89
90#define OF_CPU "PowerPC,5200@0"
91#define OF_SOC "soc5200@f0000000"
92#define OF_TBCLK (bd->bi_busfreq / 4)
93#define MV_DTB_NAME mvbc-p.dtb
94#define CONFIG_OF_STDOUT_VIA_ALIAS 1
95
96/*
97 * Supported commands
98 */
99#include <config_cmd_default.h>
100
101#define CONFIG_CMD_CACHE
102#define CONFIG_CMD_NET
103#define CONFIG_CMD_PING
104#define CONFIG_CMD_DHCP
105#define CONFIG_CMD_SDRAM
106#define CONFIG_CMD_PCI
107#define CONFIG_CMD_FPGA
André Schwarz901f5982009-07-17 14:50:24 +0200108#define CONFIG_CMD_I2C
Andre Schwarz2a293292008-07-09 18:30:44 +0200109
110#undef CONFIG_WATCHDOG
111
112#define CONFIG_BOOTP_VENDOREX
113#define CONFIG_BOOTP_SUBNETMASK
114#define CONFIG_BOOTP_GATEWAY
115#define CONFIG_BOOTP_DNS
116#define CONFIG_BOOTP_DNS2
117#define CONFIG_BOOTP_HOSTNAME
118#define CONFIG_BOOTP_BOOTFILESIZE
119#define CONFIG_BOOTP_BOOTPATH
120#define CONFIG_BOOTP_NTPSERVER
121#define CONFIG_BOOTP_RANDOM_DELAY
122#define CONFIG_BOOTP_SEND_HOSTNAME
123
124/*
125 * Autoboot
126 */
127#define CONFIG_BOOTDELAY 2
128#define CONFIG_AUTOBOOT_KEYED
129#define CONFIG_AUTOBOOT_STOP_STR "s"
130#define CONFIG_ZERO_BOOTDELAY_CHECK
131#define CONFIG_RESET_TO_RETRY 1000
132
Peter Tyserd78876c2009-09-16 21:38:10 -0500133#define CONFIG_BOOTCOMMAND "if imi ${script_addr}; \
134 then source ${script_addr}; \
135 else source ${script_addr2}; \
Andre Schwarz2a293292008-07-09 18:30:44 +0200136 fi;"
137
138#define CONFIG_BOOTARGS "root=/dev/ram ro rootfstype=squashfs"
139#define CONFIG_ENV_OVERWRITE
140
141#define XMK_STR(x) #x
142#define MK_STR(x) XMK_STR(x)
143
144#define CONFIG_EXTRA_ENV_SETTINGS \
145 "console_nr=0\0" \
146 "console=yes\0" \
147 "stdin=serial\0" \
148 "stdout=serial\0" \
149 "stderr=serial\0" \
150 "fpga=0\0" \
151 "fpgadata=" MK_STR(MV_FPGA_DATA) "\0" \
152 "fpgadatasize=" MK_STR(MV_FPGA_SIZE) "\0" \
Peter Tyserd78876c2009-09-16 21:38:10 -0500153 "script_addr=" MK_STR(MV_SCRIPT_ADDR) "\0" \
154 "script_addr2=" MK_STR(MV_SCRIPT_ADDR2) "\0" \
Andre Schwarz2a293292008-07-09 18:30:44 +0200155 "mv_kernel_addr=" MK_STR(MV_KERNEL_ADDR) "\0" \
156 "mv_kernel_addr_ram=" MK_STR(MV_KERNEL_ADDR_RAM) "\0" \
157 "mv_initrd_addr=" MK_STR(MV_INITRD_ADDR) "\0" \
158 "mv_initrd_addr_ram=" MK_STR(MV_INITRD_ADDR_RAM) "\0" \
159 "mv_initrd_length=" MK_STR(MV_INITRD_LENGTH) "\0" \
160 "mv_dtb_addr=" MK_STR(MV_DTB_ADDR) "\0" \
161 "mv_dtb_addr_ram=" MK_STR(MV_DTB_ADDR_RAM) "\0" \
162 "dtb_name=" MK_STR(MV_DTB_NAME) "\0" \
163 "mv_scratch_addr=" MK_STR(MV_SCRATCH_ADDR) "\0" \
164 "mv_scratch_length=" MK_STR(MV_SCRATCH_LENGTH) "\0" \
165 "mv_version=" U_BOOT_VERSION "\0" \
166 "dhcp_client_id=" MK_STR(MV_CI) "\0" \
167 "dhcp_vendor-class-identifier=" MK_STR(MV_VCI) "\0" \
168 "netretry=no\0" \
169 "use_static_ipaddr=no\0" \
170 "static_ipaddr=192.168.90.10\0" \
171 "static_netmask=255.255.255.0\0" \
172 "static_gateway=0.0.0.0\0" \
173 "initrd_name=uInitrd.mvbc-p-rfs\0" \
174 "zcip=no\0" \
175 "netboot=yes\0" \
176 "mvtest=Ff\0" \
177 "tried_bootfromflash=no\0" \
178 "tried_bootfromnet=no\0" \
179 "use_dhcp=yes\0" \
180 "gev_start=yes\0" \
181 "mvbcdma_debug=0\0" \
182 "mvbcia_debug=0\0" \
183 "propdev_debug=0\0" \
184 "gevss_debug=0\0" \
185 "watchdog=1\0" \
André Schwarz901f5982009-07-17 14:50:24 +0200186 "sensor_cnt=1\0" \
Andre Schwarz2a293292008-07-09 18:30:44 +0200187 ""
188
189#undef XMK_STR
190#undef MK_STR
191
192/*
193 * IPB Bus clocking configuration.
194 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200195#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK
196#define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2
Andre Schwarz2a293292008-07-09 18:30:44 +0200197
198/*
199 * Flash configuration
200 */
201#undef CONFIG_FLASH_16BIT
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200202#define CONFIG_SYS_FLASH_CFI
Jean-Christophe PLAGNIOL-VILLARD8d94c232008-08-13 01:40:42 +0200203#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200204#define CONFIG_SYS_FLASH_CFI_AMD_RESET 1
205#define CONFIG_SYS_FLASH_EMPTY_INFO
Andre Schwarz2a293292008-07-09 18:30:44 +0200206
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200207#define CONFIG_SYS_FLASH_ERASE_TOUT 50000
208#define CONFIG_SYS_FLASH_WRITE_TOUT 1000
Andre Schwarz2a293292008-07-09 18:30:44 +0200209
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200210#define CONFIG_SYS_MAX_FLASH_BANKS 1
211#define CONFIG_SYS_MAX_FLASH_SECT 256
Andre Schwarz2a293292008-07-09 18:30:44 +0200212
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200213#define CONFIG_SYS_LOWBOOT
214#define CONFIG_SYS_FLASH_BASE TEXT_BASE
215#define CONFIG_SYS_FLASH_SIZE 0x00800000
Andre Schwarz2a293292008-07-09 18:30:44 +0200216
217/*
218 * Environment settings
219 */
Jean-Christophe PLAGNIOL-VILLARD53db4cd2008-09-10 22:48:04 +0200220#define CONFIG_ENV_IS_IN_FLASH
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200221#undef CONFIG_SYS_FLASH_PROTECTION
Andre Schwarz2a293292008-07-09 18:30:44 +0200222
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200223#define CONFIG_ENV_ADDR 0xFFFE0000
224#define CONFIG_ENV_SIZE 0x10000
225#define CONFIG_ENV_SECT_SIZE 0x10000
226#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR+CONFIG_ENV_SIZE)
227#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
Andre Schwarz2a293292008-07-09 18:30:44 +0200228
229/*
230 * Memory map
231 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200232#define CONFIG_SYS_MBAR 0xF0000000
233#define CONFIG_SYS_SDRAM_BASE 0x00000000
234#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
Andre Schwarz2a293292008-07-09 18:30:44 +0200235
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200236#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
237#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE
Andre Schwarz2a293292008-07-09 18:30:44 +0200238
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200239#define CONFIG_SYS_GBL_DATA_SIZE 128
240#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
241#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Andre Schwarz2a293292008-07-09 18:30:44 +0200242
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200243#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
244#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
245#define CONFIG_SYS_RAMBOOT 1
Andre Schwarz2a293292008-07-09 18:30:44 +0200246#endif
247
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200248/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
249#define CONFIG_SYS_MONITOR_LEN (512 << 10)
250#define CONFIG_SYS_MALLOC_LEN (512 << 10)
251#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
Andre Schwarz2a293292008-07-09 18:30:44 +0200252
253/*
André Schwarz901f5982009-07-17 14:50:24 +0200254 * I2C configuration
255 */
256#define CONFIG_HARD_I2C 1
257#define CONFIG_SYS_I2C_MODULE 1
258#define CONFIG_SYS_I2C_SPEED 86000
259#define CONFIG_SYS_I2C_SLAVE 0x7F
260
261/*
Andre Schwarz2a293292008-07-09 18:30:44 +0200262 * Ethernet configuration
263 */
264#define CONFIG_NET_MULTI
265#define CONFIG_NET_RETRY_COUNT 5
266
267#define CONFIG_E1000
Wolfgang Denk9a0882b2008-07-31 13:57:20 +0200268#define CONFIG_E1000_FALLBACK_MAC { 0xb6, 0xb4, 0x45, 0xeb, 0xfb, 0xc0 }
Andre Schwarz2a293292008-07-09 18:30:44 +0200269#undef CONFIG_MPC5xxx_FEC
270#undef CONFIG_PHY_ADDR
271#define CONFIG_NETDEV eth0
272
273/*
274 * Miscellaneous configurable options
275 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200276#define CONFIG_SYS_HUSH_PARSER
Andre Schwarz2a293292008-07-09 18:30:44 +0200277#define CONFIG_CMDLINE_EDITING
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200278#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
279#undef CONFIG_SYS_LONGHELP
280#define CONFIG_SYS_PROMPT "=> "
Wolfgang Denkec1067c2008-08-12 14:54:04 +0200281#ifdef CONFIG_CMD_KGDB
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200282#define CONFIG_SYS_CBSIZE 1024
Andre Schwarz2a293292008-07-09 18:30:44 +0200283#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200284#define CONFIG_SYS_CBSIZE 256
Andre Schwarz2a293292008-07-09 18:30:44 +0200285#endif
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200286#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
287#define CONFIG_SYS_MAXARGS 16
288#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
Andre Schwarz2a293292008-07-09 18:30:44 +0200289
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200290#define CONFIG_SYS_MEMTEST_START 0x00800000
291#define CONFIG_SYS_MEMTEST_END 0x02f00000
Andre Schwarz2a293292008-07-09 18:30:44 +0200292
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200293#define CONFIG_SYS_HZ 1000
Andre Schwarz2a293292008-07-09 18:30:44 +0200294
295/* default load address */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200296#define CONFIG_SYS_LOAD_ADDR 0x02000000
Andre Schwarz2a293292008-07-09 18:30:44 +0200297/* default location for tftp and bootm */
298#define CONFIG_LOADADDR 0x00200000
299
300/*
301 * Various low-level settings
302 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200303#define CONFIG_SYS_GPS_PORT_CONFIG 0x20000004
Andre Schwarz2a293292008-07-09 18:30:44 +0200304
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200305#define CONFIG_SYS_HID0_INIT (HID0_ICE | HID0_ICFI)
306#define CONFIG_SYS_HID0_FINAL HID0_ICE
Andre Schwarz2a293292008-07-09 18:30:44 +0200307
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200308#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
309#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
310#define CONFIG_SYS_BOOTCS_CFG 0x00047800
311#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
312#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
Andre Schwarz2a293292008-07-09 18:30:44 +0200313
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200314#define CONFIG_SYS_CS_BURST 0x000000f0
315#define CONFIG_SYS_CS_DEADCYCLE 0x33333303
Andre Schwarz2a293292008-07-09 18:30:44 +0200316
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200317#define CONFIG_SYS_RESET_ADDRESS 0x00000100
Andre Schwarz2a293292008-07-09 18:30:44 +0200318
319#undef FPGA_DEBUG
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200320#undef CONFIG_SYS_FPGA_PROG_FEEDBACK
321#define CONFIG_FPGA CONFIG_SYS_ALTERA_CYCLON2
Andre Schwarz2a293292008-07-09 18:30:44 +0200322#define CONFIG_FPGA_ALTERA 1
323#define CONFIG_FPGA_CYCLON2 1
324#define CONFIG_FPGA_COUNT 1
325
326#endif