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git01.mediatek.com / filogic / uboot / c76d6162261808df8ef4693c1ca544f5983c41bd / . / arch / arm / dts / at91sam9rl.dtsi
blob: 4602cd21e17eb9bf2b9a45632fc5987185ada61b [file] [log] [blame]
Wenyou Yang59aebeb2017-04-18 13:49:38 +0800[diff] [blame]1/*
2 * at91sam9rl.dtsi - Device Tree Include file for AT91SAM9RL family SoC
3 *
4 * Copyright (C) 2014 Alexandre Belloni <alexandre.belloni@free-electrons.com>
5 *
6 * Licensed under GPLv2 or later.
7 */
8
9#include "skeleton.dtsi"
10#include <dt-bindings/pinctrl/at91.h>
11#include <dt-bindings/clock/at91.h>
12#include <dt-bindings/interrupt-controller/irq.h>
13#include <dt-bindings/gpio/gpio.h>
14#include <dt-bindings/pwm/pwm.h>
15
16/ {
17 model = "Atmel AT91SAM9RL family SoC";
18 compatible = "atmel,at91sam9rl", "atmel,at91sam9";
19 interrupt-parent = <&aic>;
20
21 aliases {
22 serial0 = &dbgu;
23 serial1 = &usart0;
24 serial2 = &usart1;
25 serial3 = &usart2;
26 serial4 = &usart3;
27 gpio0 = &pioA;
28 gpio1 = &pioB;
29 gpio2 = &pioC;
30 gpio3 = &pioD;
31 tcb0 = &tcb0;
32 i2c0 = &i2c0;
33 i2c1 = &i2c1;
34 ssc0 = &ssc0;
35 ssc1 = &ssc1;
36 pwm0 = &pwm0;
Wenyou.Yang@microchip.com5d7fd3e2017-07-21 13:40:10 +0800[diff] [blame]37 spi0 = &spi0;
Wenyou Yang59aebeb2017-04-18 13:49:38 +0800[diff] [blame]38 };
39
40 cpus {
41 #address-cells = <0>;
42 #size-cells = <0>;
43
44 cpu {
45 compatible = "arm,arm926ej-s";
46 device_type = "cpu";
47 };
48 };
49
50 memory {
51 reg = <0x20000000 0x04000000>;
52 };
53
54 clocks {
55 slow_xtal: slow_xtal {
56 compatible = "fixed-clock";
57 #clock-cells = <0>;
58 clock-frequency = <0>;
59 };
60
61 main_xtal: main_xtal {
62 compatible = "fixed-clock";
63 #clock-cells = <0>;
64 clock-frequency = <0>;
65 };
66
67 adc_op_clk: adc_op_clk{
68 compatible = "fixed-clock";
69 #clock-cells = <0>;
70 clock-frequency = <1000000>;
71 };
72 };
73
74 sram: sram@00300000 {
75 compatible = "mmio-sram";
76 reg = <0x00300000 0x10000>;
77 };
78
79 ahb {
80 compatible = "simple-bus";
81 #address-cells = <1>;
82 #size-cells = <1>;
83 ranges;
84 u-boot,dm-pre-reloc;
85
86 fb0: fb@00500000 {
87 compatible = "atmel,at91sam9rl-lcdc";
88 reg = <0x00500000 0x1000>;
89 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 3>;
90 pinctrl-names = "default";
91 pinctrl-0 = <&pinctrl_fb>;
92 clocks = <&lcd_clk>, <&lcd_clk>;
93 clock-names = "hclk", "lcdc_clk";
94 status = "disabled";
95 };
96
97 nand0: nand@40000000 {
98 compatible = "atmel,at91rm9200-nand";
99 #address-cells = <1>;
100 #size-cells = <1>;
101 reg = <0x40000000 0x10000000>,
102 <0xffffe800 0x200>;
103 atmel,nand-addr-offset = <21>;
104 atmel,nand-cmd-offset = <22>;
105 atmel,nand-has-dma;
106 pinctrl-names = "default";
107 pinctrl-0 = <&pinctrl_nand>;
108 gpios = <&pioD 17 GPIO_ACTIVE_HIGH>,
109 <&pioB 6 GPIO_ACTIVE_HIGH>,
110 <0>;
111 status = "disabled";
112 };
113
114 apb {
115 compatible = "simple-bus";
116 #address-cells = <1>;
117 #size-cells = <1>;
118 ranges;
119 u-boot,dm-pre-reloc;
120
121 tcb0: timer@fffa0000 {
122 compatible = "atmel,at91rm9200-tcb";
123 reg = <0xfffa0000 0x100>;
124 interrupts = <16 IRQ_TYPE_LEVEL_HIGH 0>,
125 <17 IRQ_TYPE_LEVEL_HIGH 0>,
126 <18 IRQ_TYPE_LEVEL_HIGH 0>;
127 clocks = <&tc0_clk>, <&tc1_clk>, <&tc2_clk>, <&clk32k>;
128 clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk";
129 };
130
131 mmc0: mmc@fffa4000 {
132 compatible = "atmel,hsmci";
133 reg = <0xfffa4000 0x600>;
134 interrupts = <10 IRQ_TYPE_LEVEL_HIGH 0>;
135 #address-cells = <1>;
136 #size-cells = <0>;
137 pinctrl-names = "default";
138 clocks = <&mci0_clk>;
139 clock-names = "mci_clk";
140 status = "disabled";
141 };
142
143 i2c0: i2c@fffa8000 {
144 compatible = "atmel,at91sam9260-i2c";
145 reg = <0xfffa8000 0x100>;
146 interrupts = <11 IRQ_TYPE_LEVEL_HIGH 6>;
147 #address-cells = <1>;
148 #size-cells = <0>;
149 clocks = <&twi0_clk>;
150 status = "disabled";
151 };
152
153 i2c1: i2c@fffac000 {
154 compatible = "atmel,at91sam9260-i2c";
155 reg = <0xfffac000 0x100>;
156 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 6>;
157 #address-cells = <1>;
158 #size-cells = <0>;
159 status = "disabled";
160 };
161
162 usart0: serial@fffb0000 {
163 compatible = "atmel,at91sam9260-usart";
164 reg = <0xfffb0000 0x200>;
165 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>;
166 atmel,use-dma-rx;
167 atmel,use-dma-tx;
168 pinctrl-names = "default";
169 pinctrl-0 = <&pinctrl_usart0>;
170 clocks = <&usart0_clk>;
171 clock-names = "usart";
172 status = "disabled";
173 };
174
175 usart1: serial@fffb4000 {
176 compatible = "atmel,at91sam9260-usart";
177 reg = <0xfffb4000 0x200>;
178 interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
179 atmel,use-dma-rx;
180 atmel,use-dma-tx;
181 pinctrl-names = "default";
182 pinctrl-0 = <&pinctrl_usart1>;
183 clocks = <&usart1_clk>;
184 clock-names = "usart";
185 status = "disabled";
186 };
187
188 usart2: serial@fffb8000 {
189 compatible = "atmel,at91sam9260-usart";
190 reg = <0xfffb8000 0x200>;
191 interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>;
192 atmel,use-dma-rx;
193 atmel,use-dma-tx;
194 pinctrl-names = "default";
195 pinctrl-0 = <&pinctrl_usart2>;
196 clocks = <&usart2_clk>;
197 clock-names = "usart";
198 status = "disabled";
199 };
200
201 usart3: serial@fffbc000 {
202 compatible = "atmel,at91sam9260-usart";
203 reg = <0xfffbc000 0x200>;
204 interrupts = <9 IRQ_TYPE_LEVEL_HIGH 5>;
205 atmel,use-dma-rx;
206 atmel,use-dma-tx;
207 pinctrl-names = "default";
208 pinctrl-0 = <&pinctrl_usart3>;
209 clocks = <&usart3_clk>;
210 clock-names = "usart";
211 status = "disabled";
212 };
213
214 ssc0: ssc@fffc0000 {
215 compatible = "atmel,at91sam9rl-ssc";
216 reg = <0xfffc0000 0x4000>;
217 interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>;
218 pinctrl-names = "default";
219 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
220 status = "disabled";
221 };
222
223 ssc1: ssc@fffc4000 {
224 compatible = "atmel,at91sam9rl-ssc";
225 reg = <0xfffc4000 0x4000>;
226 interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>;
227 pinctrl-names = "default";
228 pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
229 status = "disabled";
230 };
231
232 pwm0: pwm@fffc8000 {
233 compatible = "atmel,at91sam9rl-pwm";
234 reg = <0xfffc8000 0x300>;
235 interrupts = <19 IRQ_TYPE_LEVEL_HIGH 4>;
236 #pwm-cells = <3>;
237 clocks = <&pwm_clk>;
238 clock-names = "pwm_clk";
239 status = "disabled";
240 };
241
242 spi0: spi@fffcc000 {
243 #address-cells = <1>;
244 #size-cells = <0>;
245 compatible = "atmel,at91rm9200-spi";
246 reg = <0xfffcc000 0x200>;
247 interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>;
248 pinctrl-names = "default";
249 pinctrl-0 = <&pinctrl_spi0>;
250 clocks = <&spi0_clk>;
251 clock-names = "spi_clk";
252 status = "disabled";
253 };
254
255 adc0: adc@fffd0000 {
256 #address-cells = <1>;
257 #size-cells = <0>;
258 compatible = "atmel,at91sam9rl-adc";
259 reg = <0xfffd0000 0x100>;
260 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
261 clocks = <&adc_clk>, <&adc_op_clk>;
262 clock-names = "adc_clk", "adc_op_clk";
263 atmel,adc-use-external-triggers;
264 atmel,adc-channels-used = <0x3f>;
265 atmel,adc-vref = <3300>;
266 atmel,adc-startup-time = <40>;
267 atmel,adc-res = <8 10>;
268 atmel,adc-res-names = "lowres", "highres";
269 atmel,adc-use-res = "highres";
270
271 trigger0 {
272 trigger-name = "timer-counter-0";
273 trigger-value = <0x1>;
274 };
275 trigger1 {
276 trigger-name = "timer-counter-1";
277 trigger-value = <0x3>;
278 };
279
280 trigger2 {
281 trigger-name = "timer-counter-2";
282 trigger-value = <0x5>;
283 };
284
285 trigger3 {
286 trigger-name = "external";
287 trigger-value = <0x13>;
288 trigger-external;
289 };
290 };
291
292 usb0: gadget@fffd4000 {
293 #address-cells = <1>;
294 #size-cells = <0>;
295 compatible = "atmel,at91sam9rl-udc";
296 reg = <0x00600000 0x100000>,
297 <0xfffd4000 0x4000>;
298 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
299 clocks = <&udphs_clk>, <&utmi>;
300 clock-names = "pclk", "hclk";
301 status = "disabled";
302
303 ep@0 {
304 reg = <0>;
305 atmel,fifo-size = <64>;
306 atmel,nb-banks = <1>;
307 };
308
309 ep@1 {
310 reg = <1>;
311 atmel,fifo-size = <1024>;
312 atmel,nb-banks = <2>;
313 atmel,can-dma;
314 atmel,can-isoc;
315 };
316
317 ep@2 {
318 reg = <2>;
319 atmel,fifo-size = <1024>;
320 atmel,nb-banks = <2>;
321 atmel,can-dma;
322 atmel,can-isoc;
323 };
324
325 ep@3 {
326 reg = <3>;
327 atmel,fifo-size = <1024>;
328 atmel,nb-banks = <3>;
329 atmel,can-dma;
330 };
331
332 ep@4 {
333 reg = <4>;
334 atmel,fifo-size = <1024>;
335 atmel,nb-banks = <3>;
336 atmel,can-dma;
337 };
338
339 ep@5 {
340 reg = <5>;
341 atmel,fifo-size = <1024>;
342 atmel,nb-banks = <3>;
343 atmel,can-dma;
344 atmel,can-isoc;
345 };
346
347 ep@6 {
348 reg = <6>;
349 atmel,fifo-size = <1024>;
350 atmel,nb-banks = <3>;
351 atmel,can-dma;
352 atmel,can-isoc;
353 };
354 };
355
356 dma0: dma-controller@ffffe600 {
357 compatible = "atmel,at91sam9rl-dma";
358 reg = <0xffffe600 0x200>;
359 interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>;
360 #dma-cells = <2>;
361 clocks = <&dma0_clk>;
362 clock-names = "dma_clk";
363 };
364
365 ramc0: ramc@ffffea00 {
366 compatible = "atmel,at91sam9260-sdramc";
367 reg = <0xffffea00 0x200>;
368 };
369
370 aic: interrupt-controller@fffff000 {
371 #interrupt-cells = <3>;
372 compatible = "atmel,at91rm9200-aic";
373 interrupt-controller;
374 reg = <0xfffff000 0x200>;
375 atmel,external-irqs = <31>;
376 };
377
378 dbgu: serial@fffff200 {
379 compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
380 reg = <0xfffff200 0x200>;
381 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
382 pinctrl-names = "default";
383 pinctrl-0 = <&pinctrl_dbgu>;
384 clocks = <&mck>;
385 clock-names = "usart";
386 status = "disabled";
387 };
388
389 pinctrl@fffff400 {
390 #address-cells = <1>;
391 #size-cells = <1>;
392 compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
393 ranges = <0xfffff400 0xfffff400 0x800>;
394 reg = <0xfffff400 0x200
395 0xfffff600 0x200
396 0xfffff800 0x200
397 0xfffffa00 0x200
398 >;
399
400 atmel,mux-mask =
401 /* A B */
402 <0xffffffff 0xe05c6738>, /* pioA */
403 <0xffffffff 0x0000c780>, /* pioB */
404 <0xffffffff 0xe3ffff0e>, /* pioC */
405 <0x003fffff 0x0001ff3c>; /* pioD */
406 u-boot,dm-pre-reloc;
407
408 /* shared pinctrl settings */
409 adc0 {
410 pinctrl_adc0_ts: adc0_ts-0 {
411 atmel,pins =
412 <AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE>,
413 <AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE>,
414 <AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE>,
415 <AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE>;
416 };
417
418 pinctrl_adc0_ad0: adc0_ad0-0 {
419 atmel,pins = <AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE>;
420 };
421
422 pinctrl_adc0_ad1: adc0_ad1-0 {
423 atmel,pins = <AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE>;
424 };
425
426 pinctrl_adc0_ad2: adc0_ad2-0 {
427 atmel,pins = <AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE>;
428 };
429
430 pinctrl_adc0_ad3: adc0_ad3-0 {
431 atmel,pins = <AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE>;
432 };
433
434 pinctrl_adc0_ad4: adc0_ad4-0 {
435 atmel,pins = <AT91_PIOD 6 AT91_PERIPH_A AT91_PINCTRL_NONE>;
436 };
437
438 pinctrl_adc0_ad5: adc0_ad5-0 {
439 atmel,pins = <AT91_PIOD 7 AT91_PERIPH_A AT91_PINCTRL_NONE>;
440 };
441
442 pinctrl_adc0_adtrg: adc0_adtrg-0 {
443 atmel,pins = <AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE>;
444 };
445 };
446
447 dbgu {
448 u-boot,dm-pre-reloc;
449 pinctrl_dbgu: dbgu-0 {
450 atmel,pins =
451 <AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>,
452 <AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE>;
453 };
454 };
455
456 fb {
457 pinctrl_fb: fb-0 {
458 atmel,pins =
459 <AT91_PIOC 1 AT91_PERIPH_B AT91_PINCTRL_NONE>,
460 <AT91_PIOC 3 AT91_PERIPH_A AT91_PINCTRL_NONE>,
461 <AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE>,
462 <AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE>,
463 <AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE>,
464 <AT91_PIOC 9 AT91_PERIPH_B AT91_PINCTRL_NONE>,
465 <AT91_PIOC 10 AT91_PERIPH_B AT91_PINCTRL_NONE>,
466 <AT91_PIOC 11 AT91_PERIPH_B AT91_PINCTRL_NONE>,
467 <AT91_PIOC 12 AT91_PERIPH_B AT91_PINCTRL_NONE>,
468 <AT91_PIOC 13 AT91_PERIPH_B AT91_PINCTRL_NONE>,
469 <AT91_PIOC 15 AT91_PERIPH_B AT91_PINCTRL_NONE>,
470 <AT91_PIOC 16 AT91_PERIPH_B AT91_PINCTRL_NONE>,
471 <AT91_PIOC 17 AT91_PERIPH_B AT91_PINCTRL_NONE>,
472 <AT91_PIOC 18 AT91_PERIPH_B AT91_PINCTRL_NONE>,
473 <AT91_PIOC 19 AT91_PERIPH_B AT91_PINCTRL_NONE>,
474 <AT91_PIOC 20 AT91_PERIPH_B AT91_PINCTRL_NONE>,
475 <AT91_PIOC 21 AT91_PERIPH_B AT91_PINCTRL_NONE>,
476 <AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_NONE>,
477 <AT91_PIOC 23 AT91_PERIPH_B AT91_PINCTRL_NONE>,
478 <AT91_PIOC 24 AT91_PERIPH_B AT91_PINCTRL_NONE>,
479 <AT91_PIOC 25 AT91_PERIPH_B AT91_PINCTRL_NONE>;
480 };
481 };
482
483 i2c_gpio0 {
484 pinctrl_i2c_gpio0: i2c_gpio0-0 {
485 atmel,pins =
486 <AT91_PIOA 23 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>,
487 <AT91_PIOA 24 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>;
488 };
489 };
490
491 i2c_gpio1 {
492 pinctrl_i2c_gpio1: i2c_gpio1-0 {
493 atmel,pins =
494 <AT91_PIOD 10 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>,
495 <AT91_PIOD 11 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>;
496 };
497 };
498
499 mmc0 {
500 pinctrl_mmc0_clk: mmc0_clk-0 {
501 atmel,pins =
502 <AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE>;
503 };
504
505 pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 {
506 atmel,pins =
507 <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>,
508 <AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
509 };
510
511 pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
512 atmel,pins =
513 <AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>,
514 <AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>,
515 <AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
516 };
517 };
518
519 nand {
520 pinctrl_nand: nand-0 {
521 atmel,pins =
522 <AT91_PIOD 17 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>,
523 <AT91_PIOB 6 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;
524 };
525
526 pinctrl_nand0_ale_cle: nand_ale_cle-0 {
527 atmel,pins =
528 <AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE>,
529 <AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE>;
530 };
531
532 pinctrl_nand0_oe_we: nand_oe_we-0 {
533 atmel,pins =
534 <AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE>,
535 <AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE>;
536 };
537
538 pinctrl_nand0_cs: nand_cs-0 {
539 atmel,pins =
540 <AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE>;
541 };
542 };
543
544 pwm0 {
545 pinctrl_pwm0_pwm0_0: pwm0_pwm0-0 {
546 atmel,pins = <AT91_PIOB 8 AT91_PERIPH_B AT91_PINCTRL_NONE>;
547 };
548
549 pinctrl_pwm0_pwm0_1: pwm0_pwm0-1 {
550 atmel,pins = <AT91_PIOC 2 AT91_PERIPH_B AT91_PINCTRL_NONE>;
551 };
552
553 pinctrl_pwm0_pwm0_2: pwm0_pwm0-2 {
554 atmel,pins = <AT91_PIOD 14 AT91_PERIPH_B AT91_PINCTRL_NONE>;
555 };
556
557 pinctrl_pwm0_pwm1_0: pwm0_pwm1-0 {
558 atmel,pins = <AT91_PIOB 9 AT91_PERIPH_B AT91_PINCTRL_NONE>;
559 };
560
561 pinctrl_pwm0_pwm1_1: pwm0_pwm1-1 {
562 atmel,pins = <AT91_PIOC 3 AT91_PERIPH_B AT91_PINCTRL_NONE>;
563 };
564
565 pinctrl_pwm0_pwm1_2: pwm0_pwm1-2 {
566 atmel,pins = <AT91_PIOD 15 AT91_PERIPH_B AT91_PINCTRL_NONE>;
567 };
568
569 pinctrl_pwm0_pwm2_0: pwm0_pwm2-0 {
570 atmel,pins = <AT91_PIOD 5 AT91_PERIPH_B AT91_PINCTRL_NONE>;
571 };
572
573 pinctrl_pwm0_pwm2_1: pwm0_pwm2-1 {
574 atmel,pins = <AT91_PIOD 12 AT91_PERIPH_A AT91_PINCTRL_NONE>;
575 };
576
577 pinctrl_pwm0_pwm2_2: pwm0_pwm2-2 {
578 atmel,pins = <AT91_PIOD 16 AT91_PERIPH_B AT91_PINCTRL_NONE>;
579 };
580
581 pinctrl_pwm0_pwm3_0: pwm0_pwm3-0 {
582 atmel,pins = <AT91_PIOD 8 AT91_PERIPH_B AT91_PINCTRL_NONE>;
583 };
584
585 pinctrl_pwm0_pwm3_1: pwm0_pwm3-1 {
586 atmel,pins = <AT91_PIOD 18 AT91_PERIPH_A AT91_PINCTRL_NONE>;
587 };
588 };
589
590 spi0 {
591 pinctrl_spi0: spi0-0 {
592 atmel,pins =
593 <AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_NONE>,
594 <AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_NONE>,
595 <AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE>;
596 };
597 };
598
599 ssc0 {
600 pinctrl_ssc0_tx: ssc0_tx-0 {
601 atmel,pins =
602 <AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE>,
603 <AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE>,
604 <AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE>;
605 };
606
607 pinctrl_ssc0_rx: ssc0_rx-0 {
608 atmel,pins =
609 <AT91_PIOA 10 AT91_PERIPH_B AT91_PINCTRL_NONE>,
610 <AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_NONE>,
611 <AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE>;
612 };
613 };
614
615 ssc1 {
616 pinctrl_ssc1_tx: ssc1_tx-0 {
617 atmel,pins =
618 <AT91_PIOA 13 AT91_PERIPH_B AT91_PINCTRL_NONE>,
619 <AT91_PIOA 29 AT91_PERIPH_B AT91_PINCTRL_NONE>,
620 <AT91_PIOA 30 AT91_PERIPH_B AT91_PINCTRL_NONE>;
621 };
622
623 pinctrl_ssc1_rx: ssc1_rx-0 {
624 atmel,pins =
625 <AT91_PIOA 8 AT91_PERIPH_B AT91_PINCTRL_NONE>,
626 <AT91_PIOA 9 AT91_PERIPH_B AT91_PINCTRL_NONE>,
627 <AT91_PIOA 14 AT91_PERIPH_B AT91_PINCTRL_NONE>;
628 };
629 };
630
631 tcb0 {
632 pinctrl_tcb0_tclk0: tcb0_tclk0-0 {
633 atmel,pins = <AT91_PIOA 3 AT91_PERIPH_B AT91_PINCTRL_NONE>;
634 };
635
636 pinctrl_tcb0_tclk1: tcb0_tclk1-0 {
637 atmel,pins = <AT91_PIOC 31 AT91_PERIPH_B AT91_PINCTRL_NONE>;
638 };
639
640 pinctrl_tcb0_tclk2: tcb0_tclk2-0 {
641 atmel,pins = <AT91_PIOD 21 AT91_PERIPH_A AT91_PINCTRL_NONE>;
642 };
643
644 pinctrl_tcb0_tioa0: tcb0_tioa0-0 {
645 atmel,pins = <AT91_PIOA 4 AT91_PERIPH_B AT91_PINCTRL_NONE>;
646 };
647
648 pinctrl_tcb0_tioa1: tcb0_tioa1-0 {
649 atmel,pins = <AT91_PIOC 29 AT91_PERIPH_B AT91_PINCTRL_NONE>;
650 };
651
652 pinctrl_tcb0_tioa2: tcb0_tioa2-0 {
653 atmel,pins = <AT91_PIOD 10 AT91_PERIPH_B AT91_PINCTRL_NONE>;
654 };
655
656 pinctrl_tcb0_tiob0: tcb0_tiob0-0 {
657 atmel,pins = <AT91_PIOA 5 AT91_PERIPH_B AT91_PINCTRL_NONE>;
658 };
659
660 pinctrl_tcb0_tiob1: tcb0_tiob1-0 {
661 atmel,pins = <AT91_PIOC 30 AT91_PERIPH_B AT91_PINCTRL_NONE>;
662 };
663
664 pinctrl_tcb0_tiob2: tcb0_tiob2-0 {
665 atmel,pins = <AT91_PIOD 11 AT91_PERIPH_B AT91_PINCTRL_NONE>;
666 };
667 };
668
669 usart0 {
670 pinctrl_usart0: usart0-0 {
671 atmel,pins =
672 <AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE>,
673 <AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
674 };
675
676 pinctrl_usart0_rts: usart0_rts-0 {
677 atmel,pins =
678 <AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE>;
679 };
680
681 pinctrl_usart0_cts: usart0_cts-0 {
682 atmel,pins =
683 <AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE>;
684 };
685
686 pinctrl_usart0_dtr_dsr: usart0_dtr_dsr-0 {
687 atmel,pins =
688 <AT91_PIOD 14 AT91_PERIPH_A AT91_PINCTRL_NONE>,
689 <AT91_PIOD 15 AT91_PERIPH_A AT91_PINCTRL_NONE>;
690 };
691
692 pinctrl_usart0_dcd: usart0_dcd-0 {
693 atmel,pins =
694 <AT91_PIOD 16 AT91_PERIPH_A AT91_PINCTRL_NONE>;
695 };
696
697 pinctrl_usart0_ri: usart0_ri-0 {
698 atmel,pins =
699 <AT91_PIOD 17 AT91_PERIPH_A AT91_PINCTRL_NONE>;
700 };
701
702 pinctrl_usart0_sck: usart0_sck-0 {
703 atmel,pins =
704 <AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE>;
705 };
706 };
707
708 usart1 {
709 pinctrl_usart1: usart1-0 {
710 atmel,pins =
711 <AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>,
712 <AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE>;
713 };
714
715 pinctrl_usart1_rts: usart1_rts-0 {
716 atmel,pins =
717 <AT91_PIOA 18 AT91_PERIPH_B AT91_PINCTRL_NONE>;
718 };
719
720 pinctrl_usart1_cts: usart1_cts-0 {
721 atmel,pins =
722 <AT91_PIOA 19 AT91_PERIPH_B AT91_PINCTRL_NONE>;
723 };
724
725 pinctrl_usart1_sck: usart1_sck-0 {
726 atmel,pins =
727 <AT91_PIOD 2 AT91_PERIPH_B AT91_PINCTRL_NONE>;
728 };
729 };
730
731 usart2 {
732 pinctrl_usart2: usart2-0 {
733 atmel,pins =
734 <AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>,
735 <AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE>;
736 };
737
738 pinctrl_usart2_rts: usart2_rts-0 {
739 atmel,pins =
740 <AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_NONE>;
741 };
742
743 pinctrl_usart2_cts: usart2_cts-0 {
744 atmel,pins =
745 <AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_NONE>;
746 };
747
748 pinctrl_usart2_sck: usart2_sck-0 {
749 atmel,pins =
750 <AT91_PIOD 9 AT91_PERIPH_A AT91_PINCTRL_NONE>;
751 };
752 };
753
754 usart3 {
755 pinctrl_usart3: usart3-0 {
756 atmel,pins =
757 <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>,
758 <AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE>;
759 };
760
761 pinctrl_usart3_rts: usart3_rts-0 {
762 atmel,pins =
763 <AT91_PIOD 4 AT91_PERIPH_B AT91_PINCTRL_NONE>;
764 };
765
766 pinctrl_usart3_cts: usart3_cts-0 {
767 atmel,pins =
768 <AT91_PIOD 3 AT91_PERIPH_B AT91_PINCTRL_NONE>;
769 };
770
771 pinctrl_usart3_sck: usart3_sck-0 {
772 atmel,pins =
773 <AT91_PIOA 20 AT91_PERIPH_B AT91_PINCTRL_NONE>;
774 };
775 };
776 };
777
778 pioA: gpio@fffff400 {
779 compatible = "atmel,at91rm9200-gpio";
780 reg = <0xfffff400 0x200>;
781 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
782 #gpio-cells = <2>;
783 gpio-controller;
784 interrupt-controller;
785 #interrupt-cells = <2>;
786 clocks = <&pioA_clk>;
787 u-boot,dm-pre-reloc;
788 };
789
790 pioB: gpio@fffff600 {
791 compatible = "atmel,at91rm9200-gpio";
792 reg = <0xfffff600 0x200>;
793 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
794 #gpio-cells = <2>;
795 gpio-controller;
796 interrupt-controller;
797 #interrupt-cells = <2>;
798 clocks = <&pioB_clk>;
799 u-boot,dm-pre-reloc;
800 };
801
802 pioC: gpio@fffff800 {
803 compatible = "atmel,at91rm9200-gpio";
804 reg = <0xfffff800 0x200>;
805 interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
806 #gpio-cells = <2>;
807 gpio-controller;
808 interrupt-controller;
809 #interrupt-cells = <2>;
810 clocks = <&pioC_clk>;
811 u-boot,dm-pre-reloc;
812 };
813
814 pioD: gpio@fffffa00 {
815 compatible = "atmel,at91rm9200-gpio";
816 reg = <0xfffffa00 0x200>;
817 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>;
818 #gpio-cells = <2>;
819 gpio-controller;
820 interrupt-controller;
821 #interrupt-cells = <2>;
822 clocks = <&pioD_clk>;
823 u-boot,dm-pre-reloc;
824 };
825
826 pmc: pmc@fffffc00 {
827 compatible = "atmel,at91sam9g45-pmc", "syscon";
828 reg = <0xfffffc00 0x100>;
829 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
830 interrupt-controller;
831 #address-cells = <1>;
832 #size-cells = <0>;
833 #interrupt-cells = <1>;
834 u-boot,dm-pre-reloc;
835
836 main: mainck {
837 compatible = "atmel,at91rm9200-clk-main";
838 #clock-cells = <0>;
839 interrupts-extended = <&pmc AT91_PMC_MOSCS>;
840 clocks = <&main_xtal>;
841 };
842
843 plla: pllack@0 {
844 compatible = "atmel,at91rm9200-clk-pll";
845 #clock-cells = <0>;
846 interrupts-extended = <&pmc AT91_PMC_LOCKA>;
847 clocks = <&main>;
848 reg = <0>;
849 atmel,clk-input-range = <1000000 32000000>;
850 #atmel,pll-clk-output-range-cells = <3>;
851 atmel,pll-clk-output-ranges = <80000000 200000000 0>,
852 <190000000 240000000 2>;
853 };
854
855 utmi: utmick {
856 compatible = "atmel,at91sam9x5-clk-utmi";
857 #clock-cells = <0>;
858 interrupt-parent = <&pmc>;
859 interrupts = <AT91_PMC_LOCKU>;
860 clocks = <&main>;
861 };
862
863 mck: masterck {
864 compatible = "atmel,at91rm9200-clk-master";
865 #clock-cells = <0>;
866 interrupts-extended = <&pmc AT91_PMC_MCKRDY>;
867 clocks = <&clk32k>, <&main>, <&plla>, <&utmi>;
868 atmel,clk-output-range = <0 94000000>;
869 atmel,clk-divisors = <1 2 4 0>;
870 u-boot,dm-pre-reloc;
871 };
872
873 prog: progck {
874 compatible = "atmel,at91rm9200-clk-programmable";
875 #address-cells = <1>;
876 #size-cells = <0>;
877 interrupt-parent = <&pmc>;
878 clocks = <&clk32k>, <&main>, <&plla>, <&utmi>, <&mck>;
879
880 prog0: prog@0 {
881 #clock-cells = <0>;
882 reg = <0>;
883 interrupts = <AT91_PMC_PCKRDY(0)>;
884 };
885
886 prog1: prog@1 {
887 #clock-cells = <0>;
888 reg = <1>;
889 interrupts = <AT91_PMC_PCKRDY(1)>;
890 };
891 };
892
893 systemck {
894 compatible = "atmel,at91rm9200-clk-system";
895 #address-cells = <1>;
896 #size-cells = <0>;
897
898 pck0: pck0@8 {
899 #clock-cells = <0>;
900 reg = <8>;
901 clocks = <&prog0>;
902 };
903
904 pck1: pck1@9 {
905 #clock-cells = <0>;
906 reg = <9>;
907 clocks = <&prog1>;
908 };
909
910 };
911
912 periphck {
913 compatible = "atmel,at91rm9200-clk-peripheral";
914 #address-cells = <1>;
915 #size-cells = <0>;
916 clocks = <&mck>;
917 u-boot,dm-pre-reloc;
918
919 pioA_clk: pioA_clk@2 {
920 #clock-cells = <0>;
921 reg = <2>;
922 u-boot,dm-pre-reloc;
923 };
924
925 pioB_clk: pioB_clk@3 {
926 #clock-cells = <0>;
927 reg = <3>;
928 u-boot,dm-pre-reloc;
929 };
930
931 pioC_clk: pioC_clk@4 {
932 #clock-cells = <0>;
933 reg = <4>;
934 u-boot,dm-pre-reloc;
935 };
936
937 pioD_clk: pioD_clk@5 {
938 #clock-cells = <0>;
939 reg = <5>;
940 u-boot,dm-pre-reloc;
941 };
942
943 usart0_clk: usart0_clk@6 {
944 #clock-cells = <0>;
945 reg = <6>;
946 };
947
948 usart1_clk: usart1_clk@7 {
949 #clock-cells = <0>;
950 reg = <7>;
951 };
952
953 usart2_clk: usart2_clk@8 {
954 #clock-cells = <0>;
955 reg = <8>;
956 };
957
958 usart3_clk: usart3_clk@9 {
959 #clock-cells = <0>;
960 reg = <9>;
961 };
962
963 mci0_clk: mci0_clk@10 {
964 #clock-cells = <0>;
965 reg = <10>;
966 };
967
968 twi0_clk: twi0_clk@11 {
969 #clock-cells = <0>;
970 reg = <11>;
971 };
972
973 twi1_clk: twi1_clk@12 {
974 #clock-cells = <0>;
975 reg = <12>;
976 };
977
978 spi0_clk: spi0_clk@13 {
979 #clock-cells = <0>;
980 reg = <13>;
981 };
982
983 ssc0_clk: ssc0_clk@14 {
984 #clock-cells = <0>;
985 reg = <14>;
986 };
987
988 ssc1_clk: ssc1_clk@15 {
989 #clock-cells = <0>;
990 reg = <15>;
991 };
992
993 tc0_clk: tc0_clk@16 {
994 #clock-cells = <0>;
995 reg = <16>;
996 };
997
998 tc1_clk: tc1_clk@17 {
999 #clock-cells = <0>;
1000 reg = <17>;
1001 };
1002
1003 tc2_clk: tc2_clk@18 {
1004 #clock-cells = <0>;
1005 reg = <18>;
1006 };
1007
1008 pwm_clk: pwm_clk@19 {
1009 #clock-cells = <0>;
1010 reg = <19>;
1011 };
1012
1013 adc_clk: adc_clk@20 {
1014 #clock-cells = <0>;
1015 reg = <20>;
1016 };
1017
1018 dma0_clk: dma0_clk@21 {
1019 #clock-cells = <0>;
1020 reg = <21>;
1021 };
1022
1023 udphs_clk: udphs_clk@22 {
1024 #clock-cells = <0>;
1025 reg = <22>;
1026 };
1027
1028 lcd_clk: lcd_clk@23 {
1029 #clock-cells = <0>;
1030 reg = <23>;
1031 };
1032 };
1033 };
1034
1035 rstc@fffffd00 {
1036 compatible = "atmel,at91sam9260-rstc";
1037 reg = <0xfffffd00 0x10>;
1038 clocks = <&clk32k>;
1039 };
1040
1041 shdwc@fffffd10 {
1042 compatible = "atmel,at91sam9260-shdwc";
1043 reg = <0xfffffd10 0x10>;
1044 clocks = <&clk32k>;
1045 };
1046
1047 pit: timer@fffffd30 {
1048 compatible = "atmel,at91sam9260-pit";
1049 reg = <0xfffffd30 0xf>;
1050 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
1051 clocks = <&mck>;
1052 };
1053
1054 watchdog@fffffd40 {
1055 compatible = "atmel,at91sam9260-wdt";
1056 reg = <0xfffffd40 0x10>;
1057 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
1058 clocks = <&clk32k>;
1059 status = "disabled";
1060 };
1061
1062 sckc@fffffd50 {
1063 compatible = "atmel,at91sam9x5-sckc";
1064 reg = <0xfffffd50 0x4>;
1065
1066 slow_osc: slow_osc {
1067 compatible = "atmel,at91sam9x5-clk-slow-osc";
1068 #clock-cells = <0>;
1069 atmel,startup-time-usec = <1200000>;
1070 clocks = <&slow_xtal>;
1071 };
1072
1073 slow_rc_osc: slow_rc_osc {
1074 compatible = "atmel,at91sam9x5-clk-slow-rc-osc";
1075 #clock-cells = <0>;
1076 atmel,startup-time-usec = <75>;
1077 clock-frequency = <32768>;
1078 clock-accuracy = <50000000>;
1079 };
1080
1081 clk32k: slck {
1082 compatible = "atmel,at91sam9x5-clk-slow";
1083 #clock-cells = <0>;
1084 clocks = <&slow_rc_osc &slow_osc>;
1085 };
1086 };
1087
1088 rtc@fffffd20 {
1089 compatible = "atmel,at91sam9260-rtt";
1090 reg = <0xfffffd20 0x10>;
1091 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
1092 clocks = <&clk32k>;
1093 status = "disabled";
1094 };
1095
1096 gpbr: syscon@fffffd60 {
1097 compatible = "atmel,at91sam9260-gpbr", "syscon";
1098 reg = <0xfffffd60 0x10>;
1099 status = "disabled";
1100 };
1101
1102 rtc@fffffe00 {
1103 compatible = "atmel,at91rm9200-rtc";
1104 reg = <0xfffffe00 0x40>;
1105 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
1106 clocks = <&clk32k>;
1107 status = "disabled";
1108 };
1109
1110 };
1111 };
1112
1113 i2c-gpio-0 {
1114 compatible = "i2c-gpio";
1115 gpios = <&pioA 23 GPIO_ACTIVE_HIGH>, /* sda */
1116 <&pioA 24 GPIO_ACTIVE_HIGH>; /* scl */
1117 i2c-gpio,sda-open-drain;
1118 i2c-gpio,scl-open-drain;
1119 i2c-gpio,delay-us = <2>; /* ~100 kHz */
1120 #address-cells = <1>;
1121 #size-cells = <0>;
1122 pinctrl-names = "default";
1123 pinctrl-0 = <&pinctrl_i2c_gpio0>;
1124 status = "disabled";
1125 };
1126
1127 i2c-gpio-1 {
1128 compatible = "i2c-gpio";
1129 gpios = <&pioD 10 GPIO_ACTIVE_HIGH>, /* sda */
1130 <&pioD 11 GPIO_ACTIVE_HIGH>; /* scl */
1131 i2c-gpio,sda-open-drain;
1132 i2c-gpio,scl-open-drain;
1133 i2c-gpio,delay-us = <2>; /* ~100 kHz */
1134 #address-cells = <1>;
1135 #size-cells = <0>;
1136 pinctrl-names = "default";
1137 pinctrl-0 = <&pinctrl_i2c_gpio1>;
1138 status = "disabled";
1139 };
1140};