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git01.mediatek.com / filogic / uboot / c763cdd919e9252988ae97f67486d1f97578b20f / . / board / micronas / vct / bcu.h
blob: 19ff97844b1c7284d4666b2e9fa07f8f92757cc2 [file] [log] [blame]
Stefan Roese9182d2f2009-01-21 17:24:39 +0100[diff] [blame]1/*
2 * (C) Copyright 2009 Stefan Roese <sr@denx.de>, DENX Software Engineering
3 *
4 * Copyright (C) 2006 Micronas GmbH
5 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +0200[diff] [blame]6 * SPDX-License-Identifier: GPL-2.0+
Stefan Roese9182d2f2009-01-21 17:24:39 +0100[diff] [blame]7 */
8
9#ifndef _BCU_H
10#define _BCU_H
11
12enum bcu_tags {
13 BCU_VBV1 = 0,
14 BCU_VBV2 = 1,
15 BCU_BSS1 = 2,
16 BCU_BSS2 = 3,
17 BCU_TSD_TXT = 4,
18 BCU_TSD_SUBTITLES = 5,
19 BCU_TSD_PES_0 = 6,
20 BCU_TSD_PES_1 = 7,
21 BCU_TSD_PES_2 = 8,
22 BCU_TSD_PES_3 = 9,
23 BCU_TSIO_RECORD_0 = 10,
24 BCU_TSIO_RECORD_1 = 11,
25 BCU_TSIO_PLAYBACK_0 = 12,
26 BCU_TSIO_PLAYBACK_1 = 13,
27 BCU_SECURE_BUFFER = 14,
28 BCU_PCM1 = 15,
29 BCU_PCM2 = 16,
30 BCU_BSS_COPY = 17,
31 BCU_BSS_EXT1 = 18,
32 BCU_BSS_EXT2 = 19,
33 BCU_PCM_JINGLE = 20,
34 BCU_EBI_CPU_BUFFER = 21,
35 BCU_PCM_DELAY = 22,
36 BCU_FH_BUFFER_0 = 23,
37 BCU_FH_BUFFER_1 = 24,
38 BCU_TSD_SECTION_0 = 25,
39 BCU_TSD_SECTION_1 = 26,
40 BCU_TSD_SECTION_2 = 27,
41 BCU_TSD_SECTION_3 = 28,
42 BCU_TSD_SECTION_4 = 29,
43 BCU_TSD_SECTION_5 = 30,
44 BCU_TSD_SECTION_6 = 31,
45 BCU_TSD_SECTION_7 = 32,
46 BCU_TSD_SECTION_8 = 33,
47 BCU_TSD_SECTION_9 = 34,
48 BCU_TSD_SECTION_10 = 35,
49 BCU_TSD_SECTION_11 = 36,
50 BCU_TSD_SECTION_12 = 37,
51 BCU_TSD_SECTION_13 = 38,
52 BCU_TSD_SECTION_14 = 39,
53 BCU_TSD_SECTION_15 = 40,
54 BCU_TSD_SECTION_16 = 41,
55 BCU_TSD_SECTION_17 = 42,
56 BCU_TSD_SECTION_18 = 43,
57 BCU_TSD_SECTION_19 = 44,
58 BCU_TSD_SECTION_20 = 45,
59 BCU_TSD_SECTION_21 = 46,
60 BCU_TSD_SECTION_22 = 47,
61 BCU_TSD_SECTION_23 = 48,
62 BCU_TSD_SECTION_24 = 49,
63 BCU_TSD_SECTION_25 = 50,
64 BCU_TSD_SECTION_26 = 51,
65 BCU_TSD_SECTION_27 = 52,
66 BCU_TSD_SECTION_28 = 53,
67 BCU_TSD_SECTION_29 = 54,
68 BCU_TSD_SECTION_30 = 55,
69 BCU_TSD_SECTION_31 = 56,
70 BCU_TSD_SECTION_32 = 57,
71 BCU_TSD_SECTION_33 = 58,
72 BCU_TSD_SECTION_34 = 59,
73 BCU_TSD_SECTION_35 = 60,
74 BCU_TSD_SECTION_36 = 61,
75 BCU_TSD_SECTION_37 = 62,
76 BCU_TSD_SECTION_38 = 63,
77 BCU_TSD_SECTION_39 = 64,
78 BCU_TSD_SECTION_40 = 65,
79 BCU_TSD_SECTION_41 = 66,
80 BCU_TSD_SECTION_42 = 67,
81 BCU_TSD_SECTION_43 = 68,
82 BCU_TSD_SECTION_44 = 69,
83 BCU_TSD_SECTION_45 = 70,
84 BCU_TSD_SECTION_46 = 71,
85 BCU_TSD_SECTION_47 = 72,
86 BCU_TSD_SECTION_48 = 73,
87 BCU_TSD_SECTION_49 = 74,
88 BCU_TSD_SECTION_50 = 75,
89 BCU_TSD_SECTION_51 = 76,
90 BCU_TSD_SECTION_52 = 77,
91 BCU_TSD_SECTION_53 = 78,
92 BCU_TSIO_RECORD_2 = 79,
93 BCU_TSIO_RECORD_3 = 80,
94 BCU_TSIO_RECORD_4 = 81,
95 BCU_TSIO_RECORD_5 = 82,
96 BCU_TSIO_RECORD_6 = 83,
97 BCU_TSIO_RECORD_7 = 84,
98 BCU_TSIO_RECORD_8 = 85,
99 BCU_TSIO_RECORD_9 = 86,
100 BCU_PCM_DELAY_LINEAR = 87,
101 BCU_VD_MASTER_USER_DATA = 88,
102 BCU_VD_SLAVE_USER_DATA = 89,
103 BCU_VD_MASTER_REF0 = 90,
104 BCU_VD_MASTER_REF1 = 91,
105 BCU_VD_SLAVE_REF0 = 92,
106 BCU_VD_SLAVE_REF1 = 93,
107 BCU_VD_MASTER_DISP0_Y = 94,
108 BCU_VD_MASTER_DISP1_Y = 95,
109 BCU_VD_MASTER_DISP2_Y = 96,
110 BCU_VD_MASTER_DISP0_C = 97,
111 BCU_VD_MASTER_DISP1_C = 98,
112 BCU_VD_MASTER_DISP2_C = 99,
113 BCU_VD_SLAVE_DISP0_Y = 100,
114 BCU_VD_SLAVE_DISP1_Y = 101,
115 BCU_VD_SLAVE_DISP2_Y = 102,
116 BCU_VD_SLAVE_DISP0_C = 103,
117 BCU_VD_SLAVE_DISP1_C = 104,
118 BCU_VD_SLAVE_DISP2_C = 105,
119 BCU_CLUT_BUFFER_0 = 106,
120 BCU_CLUT_BUFFER_1 = 107,
121 BCU_OSD_FRAME_BUFFER_0 = 108,
122 BCU_OSD_FRAME_BUFFER_1 = 109,
123 BCU_GRAPHIC_FRAME_BUFFER0 = 110,
124 BCU_GRAPHIC_FRAME_BUFFER1 = 111,
125 BCU_DVP_VBI_REINSERTION = 112,
126 BCU_DVP_OSD_FRAME_BUFFER0 = 113,
127 BCU_DVP_OSD_FRAME_BUFFER1 = 114,
128 BCU_GAI_BUFFER = 115,
129 BCU_GA_SRC_BUFFER_0 = 116,
130 BCU_GA_SRC_BUFFER_1 = 117,
131 BCU_USB_BUFFER_0 = 118,
132 BCU_USB_BUFFER_1 = 119,
133 BCU_FE_3DCOMB_0 = 120,
134 BCU_FE_3DCOMB_1 = 121,
135 BCU_FE_3DCOMB_2 = 122,
136 BCU_FE_3DCOMB_3 = 123,
137 BCU_TNR_BUFFER_0 = 124,
138 BCU_TNR_BUFFER_1 = 125,
139 BCU_TNR_BUFFER_2 = 126,
140 BCU_MVAL_BUFFER = 127,
141 BCU_RC_BUFFER_0 = 128,
142 BCU_RC_BUFFER_1 = 129,
143 BCU_RC_BUFFER_2 = 130,
144 BCU_RC_BUFFER_3 = 131,
145 BCU_PIP_BUFFER_0 = 132,
146 BCU_PIP_BUFFER_1 = 133,
147 BCU_PIP_BUFFER_2 = 134,
148 BCU_PIP_BUFFER_3 = 135,
149 BCU_EWARP_BUFFER = 136,
150 BCU_OSD_BUFFER_0 = 137,
151 BCU_OSD_BUFFER_1 = 138,
152 BCU_GLOBAL_BUFFER_0 = 139,
153 BCU_GLOBAL_BUFFER_1 = 140,
154 BCU_MAX = 141
155};
156
157#endif /* _BCU_H */