| Dinh Nguyen | ad51f7c | 2012-10-04 06:46:02 +0000 | [diff] [blame] | 1 | /* |
| Pavel Machek | 5e2d70a | 2014-09-08 14:08:45 +0200 | [diff] [blame] | 2 | * Copyright (C) 2014 Marek Vasut <marex@denx.de> |
| Dinh Nguyen | ad51f7c | 2012-10-04 06:46:02 +0000 | [diff] [blame] | 3 | * |
| Wolfgang Denk | d79de1d | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 4 | * SPDX-License-Identifier: GPL-2.0+ |
| Dinh Nguyen | ad51f7c | 2012-10-04 06:46:02 +0000 | [diff] [blame] | 5 | */ |
| Pavel Machek | 5e2d70a | 2014-09-08 14:08:45 +0200 | [diff] [blame] | 6 | #ifndef __CONFIG_SOCFPGA_CYCLONE5_H__ |
| 7 | #define __CONFIG_SOCFPGA_CYCLONE5_H__ | ||||
| Dinh Nguyen | ad51f7c | 2012-10-04 06:46:02 +0000 | [diff] [blame] | 8 | |
| Dinh Nguyen | eca8b5c | 2015-11-23 17:27:17 -0600 | [diff] [blame] | 9 | #include <asm/arch/base_addr_ac5.h> |
| Dinh Nguyen | ad51f7c | 2012-10-04 06:46:02 +0000 | [diff] [blame] | 10 | |
| Marek Vasut | d4a4db1 | 2014-09-08 14:08:45 +0200 | [diff] [blame] | 11 | #define CONFIG_HW_WATCHDOG |
| Marek Vasut | bd279e3 | 2014-09-15 01:27:57 +0200 | [diff] [blame] | 12 | |
| Pavel Machek | 5e2d70a | 2014-09-08 14:08:45 +0200 | [diff] [blame] | 13 | /* Memory configurations */ |
| Marek Vasut | d4a4db1 | 2014-09-08 14:08:45 +0200 | [diff] [blame] | 14 | #define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SoCDK */ |
| Dinh Nguyen | ad51f7c | 2012-10-04 06:46:02 +0000 | [diff] [blame] | 15 | |
| Marek Vasut | d4a4db1 | 2014-09-08 14:08:45 +0200 | [diff] [blame] | 16 | /* Booting Linux */ |
| Marek Vasut | 2bff540 | 2015-07-22 06:18:19 +0200 | [diff] [blame] | 17 | #define CONFIG_LOADADDR 0x01000000 |
| Marek Vasut | d4a4db1 | 2014-09-08 14:08:45 +0200 | [diff] [blame] | 18 | #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR |
| Dinh Nguyen | ad51f7c | 2012-10-04 06:46:02 +0000 | [diff] [blame] | 19 | |
| Pavel Machek | 5e2d70a | 2014-09-08 14:08:45 +0200 | [diff] [blame] | 20 | /* Ethernet on SoC (EMAC) */ |
| 21 | #if defined(CONFIG_CMD_NET) | ||||
| Marek Vasut | d4a4db1 | 2014-09-08 14:08:45 +0200 | [diff] [blame] | 22 | #define CONFIG_PHY_MICREL |
| 23 | #define CONFIG_PHY_MICREL_KSZ9021 | ||||
| Chin Liang See | 9cd1204 | 2013-08-07 10:06:56 -0500 | [diff] [blame] | 24 | #endif |
| Pavel Machek | ce340e9 | 2014-07-14 14:14:17 +0200 | [diff] [blame] | 25 | |
| Pavel Machek | 5e2d70a | 2014-09-08 14:08:45 +0200 | [diff] [blame] | 26 | /* The rest of the configuration is shared */ |
| 27 | #include <configs/socfpga_common.h> | ||||
| Chin Liang See | 561c9d4 | 2014-06-10 01:11:04 -0500 | [diff] [blame] | 28 | |
| Pavel Machek | 5e2d70a | 2014-09-08 14:08:45 +0200 | [diff] [blame] | 29 | #endif /* __CONFIG_SOCFPGA_CYCLONE5_H__ */ |