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Nobuhiro Iwamatsu6f7d4362008-08-31 23:02:04 +09001/*
2 * Configuation settings for the Renesas Technology RSK 7203
3 *
4 * Copyright (C) 2008 Nobuhiro Iwamatsu
5 * Copyright (C) 2008 Renesas Solutions Corp.
6 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02007 * SPDX-License-Identifier: GPL-2.0+
Nobuhiro Iwamatsu6f7d4362008-08-31 23:02:04 +09008 */
9
10#ifndef __RSK7203_H
11#define __RSK7203_H
12
Nobuhiro Iwamatsu6f7d4362008-08-31 23:02:04 +090013#define CONFIG_CPU_SH7203 1
14#define CONFIG_RSK7203 1
15
Nobuhiro Iwamatsu6f7d4362008-08-31 23:02:04 +090016#define CONFIG_CMD_SDRAM
Nobuhiro Iwamatsu6f7d4362008-08-31 23:02:04 +090017
Nobuhiro Iwamatsu6f7d4362008-08-31 23:02:04 +090018#define CONFIG_BOOTARGS "console=ttySC0,115200"
19#define CONFIG_LOADADDR 0x0C100000 /* RSK7203_SDRAM_BASE + 1MB */
20
Vladimir Zapolskiy5e72b842016-11-28 00:15:30 +020021#define CONFIG_DISPLAY_BOARDINFO
Nobuhiro Iwamatsu6f7d4362008-08-31 23:02:04 +090022#undef CONFIG_SHOW_BOOT_PROGRESS
23
24/* MEMORY */
25#define RSK7203_SDRAM_BASE 0x0C000000
26#define RSK7203_FLASH_BASE_1 0x20000000 /* Non cache */
27#define RSK7203_FLASH_BANK_SIZE (4 * 1024 * 1024)
28
Nobuhiro Iwamatsu1ca69d82011-01-17 20:51:55 +090029#define CONFIG_SYS_TEXT_BASE 0x0C7C0000
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020030#define CONFIG_SYS_LONGHELP /* undef to save memory */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020031#define CONFIG_SYS_CBSIZE 256 /* Buffer size for input from the Console */
32#define CONFIG_SYS_PBSIZE 256 /* Buffer size for Console output */
33#define CONFIG_SYS_MAXARGS 16 /* max args accepted for monitor commands */
Nobuhiro Iwamatsu6f7d4362008-08-31 23:02:04 +090034/* Buffer size for Boot Arguments passed to kernel */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020035#define CONFIG_SYS_BARGSIZE 512
Nobuhiro Iwamatsu6f7d4362008-08-31 23:02:04 +090036/* List of legal baudrate settings for this board */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020037#define CONFIG_SYS_BAUDRATE_TABLE { 115200 }
Nobuhiro Iwamatsu6f7d4362008-08-31 23:02:04 +090038
39/* SCIF */
Nobuhiro Iwamatsu0852dbe2008-08-28 14:52:23 +090040#define CONFIG_SCIF_CONSOLE 1
Nobuhiro Iwamatsu6f7d4362008-08-31 23:02:04 +090041#define CONFIG_CONS_SCIF0 1
42
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020043#define CONFIG_SYS_MEMTEST_START RSK7203_SDRAM_BASE
44#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (3 * 1024 * 1024))
Nobuhiro Iwamatsu6f7d4362008-08-31 23:02:04 +090045
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020046#define CONFIG_SYS_SDRAM_BASE RSK7203_SDRAM_BASE
47#define CONFIG_SYS_SDRAM_SIZE (32 * 1024 * 1024)
Nobuhiro Iwamatsu6f7d4362008-08-31 23:02:04 +090048
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020049#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 1024 * 1024)
50#define CONFIG_SYS_MONITOR_BASE RSK7203_FLASH_BASE_1
51#define CONFIG_SYS_MONITOR_LEN (128 * 1024)
52#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020053#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
Nobuhiro Iwamatsu6f7d4362008-08-31 23:02:04 +090054
55/* FLASH */
Nobuhiro Iwamatsu0852dbe2008-08-28 14:52:23 +090056#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020057#define CONFIG_SYS_FLASH_CFI
58#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
59#undef CONFIG_SYS_FLASH_QUIET_TEST
60#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
61#define CONFIG_SYS_FLASH_BASE RSK7203_FLASH_BASE_1
62#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
63#define CONFIG_SYS_MAX_FLASH_SECT 64
64#define CONFIG_SYS_MAX_FLASH_BANKS 1
Nobuhiro Iwamatsu6f7d4362008-08-31 23:02:04 +090065
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +020066#define CONFIG_ENV_SECT_SIZE (64 * 1024)
67#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020068#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
69#define CONFIG_SYS_FLASH_ERASE_TOUT 12000
70#define CONFIG_SYS_FLASH_WRITE_TOUT 500
Nobuhiro Iwamatsu6f7d4362008-08-31 23:02:04 +090071
72/* Board Clock */
73#define CONFIG_SYS_CLK_FREQ 33333333
Nobuhiro Iwamatsue6984492013-08-21 16:11:21 +090074#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
75#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
Nobuhiro Iwamatsu6f7d4362008-08-31 23:02:04 +090076#define CMT_CLK_DIVIDER 32 /* 8 (default), 32, 128 or 512 */
Nobuhiro Iwamatsubefb5cc2014-01-08 14:57:30 +090077#define CONFIG_SH_CMT_CLK_FREQ (CONFIG_SYS_CLK_FREQ / CMT_CLK_DIVIDER)
Nobuhiro Iwamatsu6f7d4362008-08-31 23:02:04 +090078
Nobuhiro Iwamatsufe3d92e2008-10-14 11:10:59 +090079/* Network interface */
Ben Warrenfbfdd3a2009-07-20 22:01:11 -070080#define CONFIG_SMC911X
81#define CONFIG_SMC911X_16_BIT
82#define CONFIG_SMC911X_BASE (0x24000000)
Nobuhiro Iwamatsufe3d92e2008-10-14 11:10:59 +090083
Nobuhiro Iwamatsu6f7d4362008-08-31 23:02:04 +090084#endif /* __RSK7203_H */