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Nobuhiro Iwamatsu113a37e2008-06-09 13:39:57 +09001/*
2 * Copyright (C) 2008 Renesas Solutions Corp.
3 * Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
4 * Copyright (C) 2007 Kenati Technologies, Inc.
5 *
6 * board/sh7763rdp/lowlevel_init.S
7 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02008 * SPDX-License-Identifier: GPL-2.0+
Nobuhiro Iwamatsu113a37e2008-06-09 13:39:57 +09009 */
10
11#include <config.h>
Nobuhiro Iwamatsu113a37e2008-06-09 13:39:57 +090012
13#include <asm/processor.h>
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +010014#include <asm/macro.h>
Nobuhiro Iwamatsu113a37e2008-06-09 13:39:57 +090015
16 .global lowlevel_init
17
18 .text
19 .align 2
20
21lowlevel_init:
22
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +010023 write32 WDTCSR_A, WDTCSR_D /* Watchdog Control / Status Register */
Nobuhiro Iwamatsu113a37e2008-06-09 13:39:57 +090024
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +010025 write32 WDTST_A, WDTST_D /* Watchdog Stop Time Register */
Nobuhiro Iwamatsu113a37e2008-06-09 13:39:57 +090026
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +010027 write32 WDTBST_A, WDTBST_D /*
28 * 0xFFCC0008
29 * Watchdog Base Stop Time Register
30 */
Nobuhiro Iwamatsu113a37e2008-06-09 13:39:57 +090031
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +010032 write32 CCR_A, CCR_CACHE_ICI_D /* Address of Cache Control Register */
33 /* Instruction Cache Invalidate */
Nobuhiro Iwamatsu113a37e2008-06-09 13:39:57 +090034
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +010035 write32 MMUCR_A, MMU_CONTROL_TI_D /* MMU Control Register */
36 /* TI == TLB Invalidate bit */
Nobuhiro Iwamatsu113a37e2008-06-09 13:39:57 +090037
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +010038 write32 MSTPCR0_A, MSTPCR0_D /* Address of Power Control Register 0 */
Nobuhiro Iwamatsu113a37e2008-06-09 13:39:57 +090039
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +010040 write32 MSTPCR1_A, MSTPCR1_D /* Address of Power Control Register 1 */
Nobuhiro Iwamatsu113a37e2008-06-09 13:39:57 +090041
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +010042 write32 RAMCR_A, RAMCR_D
Nobuhiro Iwamatsu113a37e2008-06-09 13:39:57 +090043
Jean-Christophe PLAGNIOL-VILLARDbd963702008-12-20 19:29:48 +010044 mov.l MMSELR_A, r1
45 mov.l MMSELR_D, r0
Nobuhiro Iwamatsu113a37e2008-06-09 13:39:57 +090046 synco
47 mov.l r0, @r1
48
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +010049 mov.l @r1, r2 /* execute two reads after setting MMSELR */
Jean-Christophe PLAGNIOL-VILLARDbd963702008-12-20 19:29:48 +010050 mov.l @r1, r2
Nobuhiro Iwamatsu113a37e2008-06-09 13:39:57 +090051 synco
52
53 /* issue memory read */
Jean-Christophe PLAGNIOL-VILLARDbd963702008-12-20 19:29:48 +010054 mov.l DDRSD_START_A, r1 /* memory address to read*/
55 mov.l @r1, r0
Nobuhiro Iwamatsu113a37e2008-06-09 13:39:57 +090056 synco
57
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +010058 write32 MIM8_A, MIM8_D
Nobuhiro Iwamatsu113a37e2008-06-09 13:39:57 +090059
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +010060 write32 MIMC_A, MIMC_D1
Nobuhiro Iwamatsu113a37e2008-06-09 13:39:57 +090061
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +010062 write32 STRC_A, STRC_D
Nobuhiro Iwamatsu113a37e2008-06-09 13:39:57 +090063
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +010064 write32 SDR4_A, SDR4_D
Nobuhiro Iwamatsu113a37e2008-06-09 13:39:57 +090065
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +010066 write32 MIMC_A, MIMC_D2
Nobuhiro Iwamatsu113a37e2008-06-09 13:39:57 +090067
68 nop
69 nop
70 nop
71
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +010072 write32 SCR4_A, SCR4_D3
Nobuhiro Iwamatsu113a37e2008-06-09 13:39:57 +090073
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +010074 write32 SCR4_A, SCR4_D2
Nobuhiro Iwamatsu113a37e2008-06-09 13:39:57 +090075
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +010076 write32 SDMR02000_A, SDMR02000_D
Nobuhiro Iwamatsu113a37e2008-06-09 13:39:57 +090077
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +010078 write32 SDMR00B08_A, SDMR00B08_D
Nobuhiro Iwamatsu113a37e2008-06-09 13:39:57 +090079
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +010080 write32 SCR4_A, SCR4_D2
Nobuhiro Iwamatsu113a37e2008-06-09 13:39:57 +090081
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +010082 write32 SCR4_A, SCR4_D4
Nobuhiro Iwamatsu113a37e2008-06-09 13:39:57 +090083
84 nop
85 nop
86 nop
87 nop
88
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +010089 write32 SCR4_A, SCR4_D4
Nobuhiro Iwamatsu113a37e2008-06-09 13:39:57 +090090
91 nop
92 nop
93 nop
94 nop
95
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +010096 write32 SDMR00308_A, SDMR00308_D
Nobuhiro Iwamatsu113a37e2008-06-09 13:39:57 +090097
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +010098 write32 MIMC_A, MIMC_D3
Nobuhiro Iwamatsu113a37e2008-06-09 13:39:57 +090099
Jean-Christophe PLAGNIOL-VILLARDbd963702008-12-20 19:29:48 +0100100 mov.l SCR4_A, r1
101 mov.l SCR4_D1, r0
102 mov.l DELAY60_D, r3
Nobuhiro Iwamatsu113a37e2008-06-09 13:39:57 +0900103
104delay_loop_60:
Jean-Christophe PLAGNIOL-VILLARDbd963702008-12-20 19:29:48 +0100105 mov.l r0, @r1
Nobuhiro Iwamatsu113a37e2008-06-09 13:39:57 +0900106 dt r3
107 bf delay_loop_60
108 nop
109
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100110 write32 CCR_A, CCR_CACHE_D_2 /* Address of Cache Control Register */
Nobuhiro Iwamatsu113a37e2008-06-09 13:39:57 +0900111
112bsc_init:
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100113 write32 BCR_A, BCR_D
Nobuhiro Iwamatsu113a37e2008-06-09 13:39:57 +0900114
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100115 write32 CS0BCR_A, CS0BCR_D
Nobuhiro Iwamatsu113a37e2008-06-09 13:39:57 +0900116
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100117 write32 CS1BCR_A, CS1BCR_D
Nobuhiro Iwamatsu113a37e2008-06-09 13:39:57 +0900118
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100119 write32 CS2BCR_A, CS2BCR_D
Nobuhiro Iwamatsu113a37e2008-06-09 13:39:57 +0900120
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100121 write32 CS4BCR_A, CS4BCR_D
Nobuhiro Iwamatsu113a37e2008-06-09 13:39:57 +0900122
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100123 write32 CS5BCR_A, CS5BCR_D
Nobuhiro Iwamatsu113a37e2008-06-09 13:39:57 +0900124
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100125 write32 CS6BCR_A, CS6BCR_D
Nobuhiro Iwamatsu113a37e2008-06-09 13:39:57 +0900126
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100127 write32 CS0WCR_A, CS0WCR_D
Nobuhiro Iwamatsu113a37e2008-06-09 13:39:57 +0900128
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100129 write32 CS1WCR_A, CS1WCR_D
Nobuhiro Iwamatsu113a37e2008-06-09 13:39:57 +0900130
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100131 write32 CS2WCR_A, CS2WCR_D
Nobuhiro Iwamatsu113a37e2008-06-09 13:39:57 +0900132
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100133 write32 CS4WCR_A, CS4WCR_D
Nobuhiro Iwamatsu113a37e2008-06-09 13:39:57 +0900134
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100135 write32 CS5WCR_A, CS5WCR_D
Nobuhiro Iwamatsu113a37e2008-06-09 13:39:57 +0900136
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100137 write32 CS6WCR_A, CS6WCR_D
Nobuhiro Iwamatsu113a37e2008-06-09 13:39:57 +0900138
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100139 write32 CS5PCR_A, CS5PCR_D
Nobuhiro Iwamatsu113a37e2008-06-09 13:39:57 +0900140
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100141 write32 CS6PCR_A, CS6PCR_D
Nobuhiro Iwamatsu113a37e2008-06-09 13:39:57 +0900142
Jean-Christophe PLAGNIOL-VILLARDbd963702008-12-20 19:29:48 +0100143 mov.l DELAY200_D, r3
Nobuhiro Iwamatsu113a37e2008-06-09 13:39:57 +0900144
145delay_loop_200:
146 dt r3
147 bf delay_loop_200
148 nop
149
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100150 write16 PSEL0_A, PSEL0_D
Nobuhiro Iwamatsu113a37e2008-06-09 13:39:57 +0900151
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100152 write16 PSEL1_A, PSEL1_D
Nobuhiro Iwamatsu113a37e2008-06-09 13:39:57 +0900153
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100154 write32 ICR0_A, ICR0_D
Nobuhiro Iwamatsu113a37e2008-06-09 13:39:57 +0900155
156 stc sr, r0 /* BL bit off(init=ON) */
Jean-Christophe PLAGNIOL-VILLARDbd963702008-12-20 19:29:48 +0100157 mov.l SR_MASK_D, r1
Nobuhiro Iwamatsu113a37e2008-06-09 13:39:57 +0900158 and r1, r0
159 ldc r0, sr
160
161 rts
162 nop
163
164 .align 2
165
166DELAY60_D: .long 60
167DELAY200_D: .long 17800
168
169CCR_A: .long 0xFF00001C
170MMUCR_A: .long 0xFF000010
171RAMCR_A: .long 0xFF000074
172
173/* Low power mode control */
174MSTPCR0_A: .long 0xFFC80030
175MSTPCR1_A: .long 0xFFC80038
176
177/* RWBT */
178WDTST_A: .long 0xFFCC0000
179WDTCSR_A: .long 0xFFCC0004
180WDTBST_A: .long 0xFFCC0008
181
182/* BSC */
183MMSELR_A: .long 0xFE600020
184BCR_A: .long 0xFF801000
185CS0BCR_A: .long 0xFF802000
186CS1BCR_A: .long 0xFF802010
187CS2BCR_A: .long 0xFF802020
188CS4BCR_A: .long 0xFF802040
189CS5BCR_A: .long 0xFF802050
190CS6BCR_A: .long 0xFF802060
191CS0WCR_A: .long 0xFF802008
192CS1WCR_A: .long 0xFF802018
193CS2WCR_A: .long 0xFF802028
194CS4WCR_A: .long 0xFF802048
195CS5WCR_A: .long 0xFF802058
196CS6WCR_A: .long 0xFF802068
197CS5PCR_A: .long 0xFF802070
198CS6PCR_A: .long 0xFF802080
199DDRSD_START_A: .long 0xAC000000
200
201/* INTC */
202ICR0_A: .long 0xFFD00000
203
204/* DDR I/F */
205MIM8_A: .long 0xFE800008
206MIMC_A: .long 0xFE80000C
207SCR4_A: .long 0xFE800014
208STRC_A: .long 0xFE80001C
209SDR4_A: .long 0xFE800034
210SDMR00308_A: .long 0xFE900308
211SDMR00B08_A: .long 0xFE900B08
212SDMR02000_A: .long 0xFE902000
213
214/* GPIO */
215PSEL0_A: .long 0xFFEF0070
216PSEL1_A: .long 0xFFEF0072
217
218CCR_CACHE_ICI_D:.long 0x00000800
219CCR_CACHE_D_2: .long 0x00000103
220MMU_CONTROL_TI_D:.long 0x00000004
221RAMCR_D: .long 0x00000200
222MSTPCR0_D: .long 0x00000000
223MSTPCR1_D: .long 0x00000000
224
225MMSELR_D: .long 0xa5a50000
226BCR_D: .long 0x00000000
227CS0BCR_D: .long 0x77777770
228CS1BCR_D: .long 0x77777670
229CS2BCR_D: .long 0x77777670
230CS4BCR_D: .long 0x77777670
231CS5BCR_D: .long 0x77777670
232CS6BCR_D: .long 0x77777670
233CS0WCR_D: .long 0x7777770F
Jean-Christophe PLAGNIOL-VILLARDbd963702008-12-20 19:29:48 +0100234CS1WCR_D: .long 0x22000002
Nobuhiro Iwamatsu113a37e2008-06-09 13:39:57 +0900235CS2WCR_D: .long 0x7777770F
236CS4WCR_D: .long 0x7777770F
237CS5WCR_D: .long 0x7777770F
238CS6WCR_D: .long 0x7777770F
239CS5PCR_D: .long 0x77000000
240CS6PCR_D: .long 0x77000000
241ICR0_D: .long 0x00E00000
242MIM8_D: .long 0x00000000
243MIMC_D1: .long 0x01d10008
244MIMC_D2: .long 0x01d10009
245MIMC_D3: .long 0x01d10209
246SCR4_D1: .long 0x00000001
247SCR4_D2: .long 0x00000002
248SCR4_D3: .long 0x00000003
249SCR4_D4: .long 0x00000004
250STRC_D: .long 0x000f3980
251SDR4_D: .long 0x00000300
252SDMR00308_D: .long 0x00000000
253SDMR00B08_D: .long 0x00000000
254SDMR02000_D: .long 0x00000000
Nobuhiro Iwamatsue2c765d2010-07-22 15:29:10 +0900255PSEL0_D: .word 0x00000001
256PSEL1_D: .word 0x00000244
Nobuhiro Iwamatsu113a37e2008-06-09 13:39:57 +0900257SR_MASK_D: .long 0xEFFFFF0F
258WDTST_D: .long 0x5A000FFF
259WDTCSR_D: .long 0xA5000000
260WDTBST_D: .long 0x55000000