Nobuhiro Iwamatsu | 113a37e | 2008-06-09 13:39:57 +0900 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2008 Renesas Solutions Corp. |
| 3 | * Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> |
| 4 | * Copyright (C) 2007 Kenati Technologies, Inc. |
| 5 | * |
| 6 | * board/sh7763rdp/lowlevel_init.S |
| 7 | * |
Wolfgang Denk | d79de1d | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 8 | * SPDX-License-Identifier: GPL-2.0+ |
Nobuhiro Iwamatsu | 113a37e | 2008-06-09 13:39:57 +0900 | [diff] [blame] | 9 | */ |
| 10 | |
| 11 | #include <config.h> |
Nobuhiro Iwamatsu | 113a37e | 2008-06-09 13:39:57 +0900 | [diff] [blame] | 12 | |
| 13 | #include <asm/processor.h> |
Jean-Christophe PLAGNIOL-VILLARD | b9c2172 | 2008-12-20 19:29:49 +0100 | [diff] [blame] | 14 | #include <asm/macro.h> |
Nobuhiro Iwamatsu | 113a37e | 2008-06-09 13:39:57 +0900 | [diff] [blame] | 15 | |
| 16 | .global lowlevel_init |
| 17 | |
| 18 | .text |
| 19 | .align 2 |
| 20 | |
| 21 | lowlevel_init: |
| 22 | |
Jean-Christophe PLAGNIOL-VILLARD | b9c2172 | 2008-12-20 19:29:49 +0100 | [diff] [blame] | 23 | write32 WDTCSR_A, WDTCSR_D /* Watchdog Control / Status Register */ |
Nobuhiro Iwamatsu | 113a37e | 2008-06-09 13:39:57 +0900 | [diff] [blame] | 24 | |
Jean-Christophe PLAGNIOL-VILLARD | b9c2172 | 2008-12-20 19:29:49 +0100 | [diff] [blame] | 25 | write32 WDTST_A, WDTST_D /* Watchdog Stop Time Register */ |
Nobuhiro Iwamatsu | 113a37e | 2008-06-09 13:39:57 +0900 | [diff] [blame] | 26 | |
Jean-Christophe PLAGNIOL-VILLARD | b9c2172 | 2008-12-20 19:29:49 +0100 | [diff] [blame] | 27 | write32 WDTBST_A, WDTBST_D /* |
| 28 | * 0xFFCC0008 |
| 29 | * Watchdog Base Stop Time Register |
| 30 | */ |
Nobuhiro Iwamatsu | 113a37e | 2008-06-09 13:39:57 +0900 | [diff] [blame] | 31 | |
Jean-Christophe PLAGNIOL-VILLARD | b9c2172 | 2008-12-20 19:29:49 +0100 | [diff] [blame] | 32 | write32 CCR_A, CCR_CACHE_ICI_D /* Address of Cache Control Register */ |
| 33 | /* Instruction Cache Invalidate */ |
Nobuhiro Iwamatsu | 113a37e | 2008-06-09 13:39:57 +0900 | [diff] [blame] | 34 | |
Jean-Christophe PLAGNIOL-VILLARD | b9c2172 | 2008-12-20 19:29:49 +0100 | [diff] [blame] | 35 | write32 MMUCR_A, MMU_CONTROL_TI_D /* MMU Control Register */ |
| 36 | /* TI == TLB Invalidate bit */ |
Nobuhiro Iwamatsu | 113a37e | 2008-06-09 13:39:57 +0900 | [diff] [blame] | 37 | |
Jean-Christophe PLAGNIOL-VILLARD | b9c2172 | 2008-12-20 19:29:49 +0100 | [diff] [blame] | 38 | write32 MSTPCR0_A, MSTPCR0_D /* Address of Power Control Register 0 */ |
Nobuhiro Iwamatsu | 113a37e | 2008-06-09 13:39:57 +0900 | [diff] [blame] | 39 | |
Jean-Christophe PLAGNIOL-VILLARD | b9c2172 | 2008-12-20 19:29:49 +0100 | [diff] [blame] | 40 | write32 MSTPCR1_A, MSTPCR1_D /* Address of Power Control Register 1 */ |
Nobuhiro Iwamatsu | 113a37e | 2008-06-09 13:39:57 +0900 | [diff] [blame] | 41 | |
Jean-Christophe PLAGNIOL-VILLARD | b9c2172 | 2008-12-20 19:29:49 +0100 | [diff] [blame] | 42 | write32 RAMCR_A, RAMCR_D |
Nobuhiro Iwamatsu | 113a37e | 2008-06-09 13:39:57 +0900 | [diff] [blame] | 43 | |
Jean-Christophe PLAGNIOL-VILLARD | bd96370 | 2008-12-20 19:29:48 +0100 | [diff] [blame] | 44 | mov.l MMSELR_A, r1 |
| 45 | mov.l MMSELR_D, r0 |
Nobuhiro Iwamatsu | 113a37e | 2008-06-09 13:39:57 +0900 | [diff] [blame] | 46 | synco |
| 47 | mov.l r0, @r1 |
| 48 | |
Jean-Christophe PLAGNIOL-VILLARD | b9c2172 | 2008-12-20 19:29:49 +0100 | [diff] [blame] | 49 | mov.l @r1, r2 /* execute two reads after setting MMSELR */ |
Jean-Christophe PLAGNIOL-VILLARD | bd96370 | 2008-12-20 19:29:48 +0100 | [diff] [blame] | 50 | mov.l @r1, r2 |
Nobuhiro Iwamatsu | 113a37e | 2008-06-09 13:39:57 +0900 | [diff] [blame] | 51 | synco |
| 52 | |
| 53 | /* issue memory read */ |
Jean-Christophe PLAGNIOL-VILLARD | bd96370 | 2008-12-20 19:29:48 +0100 | [diff] [blame] | 54 | mov.l DDRSD_START_A, r1 /* memory address to read*/ |
| 55 | mov.l @r1, r0 |
Nobuhiro Iwamatsu | 113a37e | 2008-06-09 13:39:57 +0900 | [diff] [blame] | 56 | synco |
| 57 | |
Jean-Christophe PLAGNIOL-VILLARD | b9c2172 | 2008-12-20 19:29:49 +0100 | [diff] [blame] | 58 | write32 MIM8_A, MIM8_D |
Nobuhiro Iwamatsu | 113a37e | 2008-06-09 13:39:57 +0900 | [diff] [blame] | 59 | |
Jean-Christophe PLAGNIOL-VILLARD | b9c2172 | 2008-12-20 19:29:49 +0100 | [diff] [blame] | 60 | write32 MIMC_A, MIMC_D1 |
Nobuhiro Iwamatsu | 113a37e | 2008-06-09 13:39:57 +0900 | [diff] [blame] | 61 | |
Jean-Christophe PLAGNIOL-VILLARD | b9c2172 | 2008-12-20 19:29:49 +0100 | [diff] [blame] | 62 | write32 STRC_A, STRC_D |
Nobuhiro Iwamatsu | 113a37e | 2008-06-09 13:39:57 +0900 | [diff] [blame] | 63 | |
Jean-Christophe PLAGNIOL-VILLARD | b9c2172 | 2008-12-20 19:29:49 +0100 | [diff] [blame] | 64 | write32 SDR4_A, SDR4_D |
Nobuhiro Iwamatsu | 113a37e | 2008-06-09 13:39:57 +0900 | [diff] [blame] | 65 | |
Jean-Christophe PLAGNIOL-VILLARD | b9c2172 | 2008-12-20 19:29:49 +0100 | [diff] [blame] | 66 | write32 MIMC_A, MIMC_D2 |
Nobuhiro Iwamatsu | 113a37e | 2008-06-09 13:39:57 +0900 | [diff] [blame] | 67 | |
| 68 | nop |
| 69 | nop |
| 70 | nop |
| 71 | |
Jean-Christophe PLAGNIOL-VILLARD | b9c2172 | 2008-12-20 19:29:49 +0100 | [diff] [blame] | 72 | write32 SCR4_A, SCR4_D3 |
Nobuhiro Iwamatsu | 113a37e | 2008-06-09 13:39:57 +0900 | [diff] [blame] | 73 | |
Jean-Christophe PLAGNIOL-VILLARD | b9c2172 | 2008-12-20 19:29:49 +0100 | [diff] [blame] | 74 | write32 SCR4_A, SCR4_D2 |
Nobuhiro Iwamatsu | 113a37e | 2008-06-09 13:39:57 +0900 | [diff] [blame] | 75 | |
Jean-Christophe PLAGNIOL-VILLARD | b9c2172 | 2008-12-20 19:29:49 +0100 | [diff] [blame] | 76 | write32 SDMR02000_A, SDMR02000_D |
Nobuhiro Iwamatsu | 113a37e | 2008-06-09 13:39:57 +0900 | [diff] [blame] | 77 | |
Jean-Christophe PLAGNIOL-VILLARD | b9c2172 | 2008-12-20 19:29:49 +0100 | [diff] [blame] | 78 | write32 SDMR00B08_A, SDMR00B08_D |
Nobuhiro Iwamatsu | 113a37e | 2008-06-09 13:39:57 +0900 | [diff] [blame] | 79 | |
Jean-Christophe PLAGNIOL-VILLARD | b9c2172 | 2008-12-20 19:29:49 +0100 | [diff] [blame] | 80 | write32 SCR4_A, SCR4_D2 |
Nobuhiro Iwamatsu | 113a37e | 2008-06-09 13:39:57 +0900 | [diff] [blame] | 81 | |
Jean-Christophe PLAGNIOL-VILLARD | b9c2172 | 2008-12-20 19:29:49 +0100 | [diff] [blame] | 82 | write32 SCR4_A, SCR4_D4 |
Nobuhiro Iwamatsu | 113a37e | 2008-06-09 13:39:57 +0900 | [diff] [blame] | 83 | |
| 84 | nop |
| 85 | nop |
| 86 | nop |
| 87 | nop |
| 88 | |
Jean-Christophe PLAGNIOL-VILLARD | b9c2172 | 2008-12-20 19:29:49 +0100 | [diff] [blame] | 89 | write32 SCR4_A, SCR4_D4 |
Nobuhiro Iwamatsu | 113a37e | 2008-06-09 13:39:57 +0900 | [diff] [blame] | 90 | |
| 91 | nop |
| 92 | nop |
| 93 | nop |
| 94 | nop |
| 95 | |
Jean-Christophe PLAGNIOL-VILLARD | b9c2172 | 2008-12-20 19:29:49 +0100 | [diff] [blame] | 96 | write32 SDMR00308_A, SDMR00308_D |
Nobuhiro Iwamatsu | 113a37e | 2008-06-09 13:39:57 +0900 | [diff] [blame] | 97 | |
Jean-Christophe PLAGNIOL-VILLARD | b9c2172 | 2008-12-20 19:29:49 +0100 | [diff] [blame] | 98 | write32 MIMC_A, MIMC_D3 |
Nobuhiro Iwamatsu | 113a37e | 2008-06-09 13:39:57 +0900 | [diff] [blame] | 99 | |
Jean-Christophe PLAGNIOL-VILLARD | bd96370 | 2008-12-20 19:29:48 +0100 | [diff] [blame] | 100 | mov.l SCR4_A, r1 |
| 101 | mov.l SCR4_D1, r0 |
| 102 | mov.l DELAY60_D, r3 |
Nobuhiro Iwamatsu | 113a37e | 2008-06-09 13:39:57 +0900 | [diff] [blame] | 103 | |
| 104 | delay_loop_60: |
Jean-Christophe PLAGNIOL-VILLARD | bd96370 | 2008-12-20 19:29:48 +0100 | [diff] [blame] | 105 | mov.l r0, @r1 |
Nobuhiro Iwamatsu | 113a37e | 2008-06-09 13:39:57 +0900 | [diff] [blame] | 106 | dt r3 |
| 107 | bf delay_loop_60 |
| 108 | nop |
| 109 | |
Jean-Christophe PLAGNIOL-VILLARD | b9c2172 | 2008-12-20 19:29:49 +0100 | [diff] [blame] | 110 | write32 CCR_A, CCR_CACHE_D_2 /* Address of Cache Control Register */ |
Nobuhiro Iwamatsu | 113a37e | 2008-06-09 13:39:57 +0900 | [diff] [blame] | 111 | |
| 112 | bsc_init: |
Jean-Christophe PLAGNIOL-VILLARD | b9c2172 | 2008-12-20 19:29:49 +0100 | [diff] [blame] | 113 | write32 BCR_A, BCR_D |
Nobuhiro Iwamatsu | 113a37e | 2008-06-09 13:39:57 +0900 | [diff] [blame] | 114 | |
Jean-Christophe PLAGNIOL-VILLARD | b9c2172 | 2008-12-20 19:29:49 +0100 | [diff] [blame] | 115 | write32 CS0BCR_A, CS0BCR_D |
Nobuhiro Iwamatsu | 113a37e | 2008-06-09 13:39:57 +0900 | [diff] [blame] | 116 | |
Jean-Christophe PLAGNIOL-VILLARD | b9c2172 | 2008-12-20 19:29:49 +0100 | [diff] [blame] | 117 | write32 CS1BCR_A, CS1BCR_D |
Nobuhiro Iwamatsu | 113a37e | 2008-06-09 13:39:57 +0900 | [diff] [blame] | 118 | |
Jean-Christophe PLAGNIOL-VILLARD | b9c2172 | 2008-12-20 19:29:49 +0100 | [diff] [blame] | 119 | write32 CS2BCR_A, CS2BCR_D |
Nobuhiro Iwamatsu | 113a37e | 2008-06-09 13:39:57 +0900 | [diff] [blame] | 120 | |
Jean-Christophe PLAGNIOL-VILLARD | b9c2172 | 2008-12-20 19:29:49 +0100 | [diff] [blame] | 121 | write32 CS4BCR_A, CS4BCR_D |
Nobuhiro Iwamatsu | 113a37e | 2008-06-09 13:39:57 +0900 | [diff] [blame] | 122 | |
Jean-Christophe PLAGNIOL-VILLARD | b9c2172 | 2008-12-20 19:29:49 +0100 | [diff] [blame] | 123 | write32 CS5BCR_A, CS5BCR_D |
Nobuhiro Iwamatsu | 113a37e | 2008-06-09 13:39:57 +0900 | [diff] [blame] | 124 | |
Jean-Christophe PLAGNIOL-VILLARD | b9c2172 | 2008-12-20 19:29:49 +0100 | [diff] [blame] | 125 | write32 CS6BCR_A, CS6BCR_D |
Nobuhiro Iwamatsu | 113a37e | 2008-06-09 13:39:57 +0900 | [diff] [blame] | 126 | |
Jean-Christophe PLAGNIOL-VILLARD | b9c2172 | 2008-12-20 19:29:49 +0100 | [diff] [blame] | 127 | write32 CS0WCR_A, CS0WCR_D |
Nobuhiro Iwamatsu | 113a37e | 2008-06-09 13:39:57 +0900 | [diff] [blame] | 128 | |
Jean-Christophe PLAGNIOL-VILLARD | b9c2172 | 2008-12-20 19:29:49 +0100 | [diff] [blame] | 129 | write32 CS1WCR_A, CS1WCR_D |
Nobuhiro Iwamatsu | 113a37e | 2008-06-09 13:39:57 +0900 | [diff] [blame] | 130 | |
Jean-Christophe PLAGNIOL-VILLARD | b9c2172 | 2008-12-20 19:29:49 +0100 | [diff] [blame] | 131 | write32 CS2WCR_A, CS2WCR_D |
Nobuhiro Iwamatsu | 113a37e | 2008-06-09 13:39:57 +0900 | [diff] [blame] | 132 | |
Jean-Christophe PLAGNIOL-VILLARD | b9c2172 | 2008-12-20 19:29:49 +0100 | [diff] [blame] | 133 | write32 CS4WCR_A, CS4WCR_D |
Nobuhiro Iwamatsu | 113a37e | 2008-06-09 13:39:57 +0900 | [diff] [blame] | 134 | |
Jean-Christophe PLAGNIOL-VILLARD | b9c2172 | 2008-12-20 19:29:49 +0100 | [diff] [blame] | 135 | write32 CS5WCR_A, CS5WCR_D |
Nobuhiro Iwamatsu | 113a37e | 2008-06-09 13:39:57 +0900 | [diff] [blame] | 136 | |
Jean-Christophe PLAGNIOL-VILLARD | b9c2172 | 2008-12-20 19:29:49 +0100 | [diff] [blame] | 137 | write32 CS6WCR_A, CS6WCR_D |
Nobuhiro Iwamatsu | 113a37e | 2008-06-09 13:39:57 +0900 | [diff] [blame] | 138 | |
Jean-Christophe PLAGNIOL-VILLARD | b9c2172 | 2008-12-20 19:29:49 +0100 | [diff] [blame] | 139 | write32 CS5PCR_A, CS5PCR_D |
Nobuhiro Iwamatsu | 113a37e | 2008-06-09 13:39:57 +0900 | [diff] [blame] | 140 | |
Jean-Christophe PLAGNIOL-VILLARD | b9c2172 | 2008-12-20 19:29:49 +0100 | [diff] [blame] | 141 | write32 CS6PCR_A, CS6PCR_D |
Nobuhiro Iwamatsu | 113a37e | 2008-06-09 13:39:57 +0900 | [diff] [blame] | 142 | |
Jean-Christophe PLAGNIOL-VILLARD | bd96370 | 2008-12-20 19:29:48 +0100 | [diff] [blame] | 143 | mov.l DELAY200_D, r3 |
Nobuhiro Iwamatsu | 113a37e | 2008-06-09 13:39:57 +0900 | [diff] [blame] | 144 | |
| 145 | delay_loop_200: |
| 146 | dt r3 |
| 147 | bf delay_loop_200 |
| 148 | nop |
| 149 | |
Jean-Christophe PLAGNIOL-VILLARD | b9c2172 | 2008-12-20 19:29:49 +0100 | [diff] [blame] | 150 | write16 PSEL0_A, PSEL0_D |
Nobuhiro Iwamatsu | 113a37e | 2008-06-09 13:39:57 +0900 | [diff] [blame] | 151 | |
Jean-Christophe PLAGNIOL-VILLARD | b9c2172 | 2008-12-20 19:29:49 +0100 | [diff] [blame] | 152 | write16 PSEL1_A, PSEL1_D |
Nobuhiro Iwamatsu | 113a37e | 2008-06-09 13:39:57 +0900 | [diff] [blame] | 153 | |
Jean-Christophe PLAGNIOL-VILLARD | b9c2172 | 2008-12-20 19:29:49 +0100 | [diff] [blame] | 154 | write32 ICR0_A, ICR0_D |
Nobuhiro Iwamatsu | 113a37e | 2008-06-09 13:39:57 +0900 | [diff] [blame] | 155 | |
| 156 | stc sr, r0 /* BL bit off(init=ON) */ |
Jean-Christophe PLAGNIOL-VILLARD | bd96370 | 2008-12-20 19:29:48 +0100 | [diff] [blame] | 157 | mov.l SR_MASK_D, r1 |
Nobuhiro Iwamatsu | 113a37e | 2008-06-09 13:39:57 +0900 | [diff] [blame] | 158 | and r1, r0 |
| 159 | ldc r0, sr |
| 160 | |
| 161 | rts |
| 162 | nop |
| 163 | |
| 164 | .align 2 |
| 165 | |
| 166 | DELAY60_D: .long 60 |
| 167 | DELAY200_D: .long 17800 |
| 168 | |
| 169 | CCR_A: .long 0xFF00001C |
| 170 | MMUCR_A: .long 0xFF000010 |
| 171 | RAMCR_A: .long 0xFF000074 |
| 172 | |
| 173 | /* Low power mode control */ |
| 174 | MSTPCR0_A: .long 0xFFC80030 |
| 175 | MSTPCR1_A: .long 0xFFC80038 |
| 176 | |
| 177 | /* RWBT */ |
| 178 | WDTST_A: .long 0xFFCC0000 |
| 179 | WDTCSR_A: .long 0xFFCC0004 |
| 180 | WDTBST_A: .long 0xFFCC0008 |
| 181 | |
| 182 | /* BSC */ |
| 183 | MMSELR_A: .long 0xFE600020 |
| 184 | BCR_A: .long 0xFF801000 |
| 185 | CS0BCR_A: .long 0xFF802000 |
| 186 | CS1BCR_A: .long 0xFF802010 |
| 187 | CS2BCR_A: .long 0xFF802020 |
| 188 | CS4BCR_A: .long 0xFF802040 |
| 189 | CS5BCR_A: .long 0xFF802050 |
| 190 | CS6BCR_A: .long 0xFF802060 |
| 191 | CS0WCR_A: .long 0xFF802008 |
| 192 | CS1WCR_A: .long 0xFF802018 |
| 193 | CS2WCR_A: .long 0xFF802028 |
| 194 | CS4WCR_A: .long 0xFF802048 |
| 195 | CS5WCR_A: .long 0xFF802058 |
| 196 | CS6WCR_A: .long 0xFF802068 |
| 197 | CS5PCR_A: .long 0xFF802070 |
| 198 | CS6PCR_A: .long 0xFF802080 |
| 199 | DDRSD_START_A: .long 0xAC000000 |
| 200 | |
| 201 | /* INTC */ |
| 202 | ICR0_A: .long 0xFFD00000 |
| 203 | |
| 204 | /* DDR I/F */ |
| 205 | MIM8_A: .long 0xFE800008 |
| 206 | MIMC_A: .long 0xFE80000C |
| 207 | SCR4_A: .long 0xFE800014 |
| 208 | STRC_A: .long 0xFE80001C |
| 209 | SDR4_A: .long 0xFE800034 |
| 210 | SDMR00308_A: .long 0xFE900308 |
| 211 | SDMR00B08_A: .long 0xFE900B08 |
| 212 | SDMR02000_A: .long 0xFE902000 |
| 213 | |
| 214 | /* GPIO */ |
| 215 | PSEL0_A: .long 0xFFEF0070 |
| 216 | PSEL1_A: .long 0xFFEF0072 |
| 217 | |
| 218 | CCR_CACHE_ICI_D:.long 0x00000800 |
| 219 | CCR_CACHE_D_2: .long 0x00000103 |
| 220 | MMU_CONTROL_TI_D:.long 0x00000004 |
| 221 | RAMCR_D: .long 0x00000200 |
| 222 | MSTPCR0_D: .long 0x00000000 |
| 223 | MSTPCR1_D: .long 0x00000000 |
| 224 | |
| 225 | MMSELR_D: .long 0xa5a50000 |
| 226 | BCR_D: .long 0x00000000 |
| 227 | CS0BCR_D: .long 0x77777770 |
| 228 | CS1BCR_D: .long 0x77777670 |
| 229 | CS2BCR_D: .long 0x77777670 |
| 230 | CS4BCR_D: .long 0x77777670 |
| 231 | CS5BCR_D: .long 0x77777670 |
| 232 | CS6BCR_D: .long 0x77777670 |
| 233 | CS0WCR_D: .long 0x7777770F |
Jean-Christophe PLAGNIOL-VILLARD | bd96370 | 2008-12-20 19:29:48 +0100 | [diff] [blame] | 234 | CS1WCR_D: .long 0x22000002 |
Nobuhiro Iwamatsu | 113a37e | 2008-06-09 13:39:57 +0900 | [diff] [blame] | 235 | CS2WCR_D: .long 0x7777770F |
| 236 | CS4WCR_D: .long 0x7777770F |
| 237 | CS5WCR_D: .long 0x7777770F |
| 238 | CS6WCR_D: .long 0x7777770F |
| 239 | CS5PCR_D: .long 0x77000000 |
| 240 | CS6PCR_D: .long 0x77000000 |
| 241 | ICR0_D: .long 0x00E00000 |
| 242 | MIM8_D: .long 0x00000000 |
| 243 | MIMC_D1: .long 0x01d10008 |
| 244 | MIMC_D2: .long 0x01d10009 |
| 245 | MIMC_D3: .long 0x01d10209 |
| 246 | SCR4_D1: .long 0x00000001 |
| 247 | SCR4_D2: .long 0x00000002 |
| 248 | SCR4_D3: .long 0x00000003 |
| 249 | SCR4_D4: .long 0x00000004 |
| 250 | STRC_D: .long 0x000f3980 |
| 251 | SDR4_D: .long 0x00000300 |
| 252 | SDMR00308_D: .long 0x00000000 |
| 253 | SDMR00B08_D: .long 0x00000000 |
| 254 | SDMR02000_D: .long 0x00000000 |
Nobuhiro Iwamatsu | e2c765d | 2010-07-22 15:29:10 +0900 | [diff] [blame] | 255 | PSEL0_D: .word 0x00000001 |
| 256 | PSEL1_D: .word 0x00000244 |
Nobuhiro Iwamatsu | 113a37e | 2008-06-09 13:39:57 +0900 | [diff] [blame] | 257 | SR_MASK_D: .long 0xEFFFFF0F |
| 258 | WDTST_D: .long 0x5A000FFF |
| 259 | WDTCSR_D: .long 0xA5000000 |
| 260 | WDTBST_D: .long 0x55000000 |