| Stefan Roese | 1c60fe7 | 2014-11-07 12:37:49 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2012 |
| 3 | * Altera Corporation <www.altera.com> |
| 4 | * |
| 5 | * SPDX-License-Identifier: GPL-2.0+ |
| 6 | */ |
| 7 | |
| 8 | #ifndef __CADENCE_QSPI_H__ |
| 9 | #define __CADENCE_QSPI_H__ |
| 10 | |
| 11 | #define CQSPI_IS_ADDR(cmd_len) (cmd_len > 1 ? 1 : 0) |
| 12 | |
| 13 | #define CQSPI_NO_DECODER_MAX_CS 4 |
| 14 | #define CQSPI_DECODER_MAX_CS 16 |
| 15 | #define CQSPI_READ_CAPTURE_MAX_DELAY 16 |
| 16 | |
| 17 | struct cadence_spi_platdata { |
| 18 | unsigned int max_hz; |
| 19 | void *regbase; |
| 20 | void *ahbbase; |
| Jason Rush | 1b4df5e | 2018-01-23 17:13:09 -0600 | [diff] [blame] | 21 | bool is_decoded_cs; |
| 22 | u32 fifo_depth; |
| 23 | u32 fifo_width; |
| 24 | u32 trigger_address; |
| Stefan Roese | 1c60fe7 | 2014-11-07 12:37:49 +0100 | [diff] [blame] | 25 | |
| Jason Rush | 1b4df5e | 2018-01-23 17:13:09 -0600 | [diff] [blame] | 26 | /* Flash parameters */ |
| Stefan Roese | 1c60fe7 | 2014-11-07 12:37:49 +0100 | [diff] [blame] | 27 | u32 page_size; |
| 28 | u32 block_size; |
| 29 | u32 tshsl_ns; |
| 30 | u32 tsd2d_ns; |
| 31 | u32 tchsh_ns; |
| 32 | u32 tslch_ns; |
| Stefan Roese | 1c60fe7 | 2014-11-07 12:37:49 +0100 | [diff] [blame] | 33 | }; |
| 34 | |
| 35 | struct cadence_spi_priv { |
| 36 | void *regbase; |
| 37 | void *ahbbase; |
| 38 | size_t cmd_len; |
| 39 | u8 cmd_buf[32]; |
| 40 | size_t data_len; |
| 41 | |
| 42 | int qspi_is_init; |
| 43 | unsigned int qspi_calibrated_hz; |
| 44 | unsigned int qspi_calibrated_cs; |
| Chin Liang See | 36431f9 | 2015-10-17 08:31:55 -0500 | [diff] [blame] | 45 | unsigned int previous_hz; |
| Stefan Roese | 1c60fe7 | 2014-11-07 12:37:49 +0100 | [diff] [blame] | 46 | }; |
| 47 | |
| 48 | /* Functions call declaration */ |
| 49 | void cadence_qspi_apb_controller_init(struct cadence_spi_platdata *plat); |
| 50 | void cadence_qspi_apb_controller_enable(void *reg_base_addr); |
| 51 | void cadence_qspi_apb_controller_disable(void *reg_base_addr); |
| 52 | |
| 53 | int cadence_qspi_apb_command_read(void *reg_base_addr, |
| 54 | unsigned int cmdlen, const u8 *cmdbuf, unsigned int rxlen, u8 *rxbuf); |
| 55 | int cadence_qspi_apb_command_write(void *reg_base_addr, |
| 56 | unsigned int cmdlen, const u8 *cmdbuf, |
| 57 | unsigned int txlen, const u8 *txbuf); |
| 58 | |
| 59 | int cadence_qspi_apb_indirect_read_setup(struct cadence_spi_platdata *plat, |
| Vignesh R | 4ca6019 | 2016-07-06 10:20:56 +0530 | [diff] [blame] | 60 | unsigned int cmdlen, unsigned int rx_width, const u8 *cmdbuf); |
| Stefan Roese | 1c60fe7 | 2014-11-07 12:37:49 +0100 | [diff] [blame] | 61 | int cadence_qspi_apb_indirect_read_execute(struct cadence_spi_platdata *plat, |
| 62 | unsigned int rxlen, u8 *rxbuf); |
| 63 | int cadence_qspi_apb_indirect_write_setup(struct cadence_spi_platdata *plat, |
| 64 | unsigned int cmdlen, const u8 *cmdbuf); |
| 65 | int cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata *plat, |
| 66 | unsigned int txlen, const u8 *txbuf); |
| 67 | |
| 68 | void cadence_qspi_apb_chipselect(void *reg_base, |
| 69 | unsigned int chip_select, unsigned int decoder_enable); |
| Phil Edworthy | eef2edc | 2016-11-29 12:58:31 +0000 | [diff] [blame] | 70 | void cadence_qspi_apb_set_clk_mode(void *reg_base, uint mode); |
| Stefan Roese | 1c60fe7 | 2014-11-07 12:37:49 +0100 | [diff] [blame] | 71 | void cadence_qspi_apb_config_baudrate_div(void *reg_base, |
| 72 | unsigned int ref_clk_hz, unsigned int sclk_hz); |
| 73 | void cadence_qspi_apb_delay(void *reg_base, |
| 74 | unsigned int ref_clk, unsigned int sclk_hz, |
| 75 | unsigned int tshsl_ns, unsigned int tsd2d_ns, |
| 76 | unsigned int tchsh_ns, unsigned int tslch_ns); |
| 77 | void cadence_qspi_apb_enter_xip(void *reg_base, char xip_dummy); |
| 78 | void cadence_qspi_apb_readdata_capture(void *reg_base, |
| 79 | unsigned int bypass, unsigned int delay); |
| 80 | |
| 81 | #endif /* __CADENCE_QSPI_H__ */ |