| John Rigby | 25a3362 | 2011-04-19 10:42:42 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2009 ST-Ericsson SA |
| 3 | * |
| 4 | * Copied from the Linux version: |
| 5 | * Author: Kumar Sanghvi <kumar.sanghvi@stericsson.com> |
| 6 | * |
| Wolfgang Denk | d79de1d | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 7 | * SPDX-License-Identifier: GPL-2.0+ |
| John Rigby | 25a3362 | 2011-04-19 10:42:42 +0000 | [diff] [blame] | 8 | */ |
| 9 | #ifndef __MACH_PRCMU_FW_V1_H |
| 10 | #define __MACH_PRCMU_FW_V1_H |
| 11 | |
| 12 | #define AP_EXECUTE 2 |
| 13 | #define I2CREAD 1 |
| 14 | #define I2C_WR_OK 1 |
| 15 | #define I2C_RD_OK 2 |
| 16 | #define I2CWRITE 0 |
| 17 | |
| Mathieu J. Poirier | 6579898 | 2012-07-31 08:59:25 +0000 | [diff] [blame] | 18 | #define PRCMU_BASE U8500_PRCMU_BASE |
| Mathieu J. Poirier | a9b226c | 2012-07-31 08:59:27 +0000 | [diff] [blame] | 19 | #define PRCMU_BASE_TCDM U8500_PRCMU_TCDM_BASE |
| Mathieu J. Poirier | 6579898 | 2012-07-31 08:59:25 +0000 | [diff] [blame] | 20 | #define PRCM_UARTCLK_MGT_REG (PRCMU_BASE + 0x018) |
| 21 | #define PRCM_MSPCLK_MGT_REG (PRCMU_BASE + 0x01C) |
| 22 | #define PRCM_I2CCLK_MGT_REG (PRCMU_BASE + 0x020) |
| 23 | #define PRCM_SDMMCCLK_MGT_REG (PRCMU_BASE + 0x024) |
| 24 | #define PRCM_PER1CLK_MGT_REG (PRCMU_BASE + 0x02C) |
| 25 | #define PRCM_PER2CLK_MGT_REG (PRCMU_BASE + 0x030) |
| 26 | #define PRCM_PER3CLK_MGT_REG (PRCMU_BASE + 0x034) |
| 27 | #define PRCM_PER5CLK_MGT_REG (PRCMU_BASE + 0x038) |
| 28 | #define PRCM_PER6CLK_MGT_REG (PRCMU_BASE + 0x03C) |
| 29 | #define PRCM_PER7CLK_MGT_REG (PRCMU_BASE + 0x040) |
| Mathieu J. Poirier | a9b226c | 2012-07-31 08:59:27 +0000 | [diff] [blame] | 30 | #define PRCM_MBOX_CPU_VAL (PRCMU_BASE + 0x0FC) |
| 31 | #define PRCM_MBOX_CPU_SET (PRCMU_BASE + 0x100) |
| John Rigby | 25a3362 | 2011-04-19 10:42:42 +0000 | [diff] [blame] | 32 | |
| Mathieu J. Poirier | 6579898 | 2012-07-31 08:59:25 +0000 | [diff] [blame] | 33 | #define PRCM_ARM_IT1_CLEAR (PRCMU_BASE + 0x48C) |
| Mathieu J. Poirier | a9b226c | 2012-07-31 08:59:27 +0000 | [diff] [blame] | 34 | #define PRCM_ARM_IT1_VAL (PRCMU_BASE + 0x494) |
| Mathieu J. Poirier | 6579898 | 2012-07-31 08:59:25 +0000 | [diff] [blame] | 35 | #define PRCM_TCR (PRCMU_BASE + 0x1C8) |
| Mathieu J. Poirier | a9b226c | 2012-07-31 08:59:27 +0000 | [diff] [blame] | 36 | #define PRCM_REQ_MB5 (PRCMU_BASE_TCDM + 0xE44) |
| 37 | #define PRCM_ACK_MB5 (PRCMU_BASE_TCDM + 0xDF4) |
| 38 | #define PRCM_XP70_CUR_PWR_STATE (PRCMU_BASE_TCDM + 0xFFC) |
| John Rigby | 25a3362 | 2011-04-19 10:42:42 +0000 | [diff] [blame] | 39 | /* Mailbox 5 Requests */ |
| 40 | #define PRCM_REQ_MB5_I2COPTYPE_REG (PRCM_REQ_MB5 + 0x0) |
| 41 | #define PRCM_REQ_MB5_BIT_FIELDS (PRCM_REQ_MB5 + 0x1) |
| 42 | #define PRCM_REQ_MB5_I2CSLAVE (PRCM_REQ_MB5 + 0x2) |
| 43 | #define PRCM_REQ_MB5_I2CVAL (PRCM_REQ_MB5 + 0x3) |
| 44 | |
| 45 | /* Mailbox 5 ACKs */ |
| 46 | #define PRCM_ACK_MB5_STATUS (PRCM_ACK_MB5 + 0x1) |
| 47 | #define PRCM_ACK_MB5_SLAVE (PRCM_ACK_MB5 + 0x2) |
| 48 | #define PRCM_ACK_MB5_VAL (PRCM_ACK_MB5 + 0x3) |
| 49 | |
| 50 | #define LOW_POWER_WAKEUP 1 |
| 51 | #define EXE_WAKEUP 0 |
| 52 | |
| 53 | #define REQ_MB5 5 |
| 54 | |
| Mathieu J. Poirier | cc1bb79 | 2012-07-31 08:59:28 +0000 | [diff] [blame] | 55 | #define ab8500_read prcmu_i2c_read |
| 56 | #define ab8500_write prcmu_i2c_write |
| 57 | |
| 58 | int prcmu_i2c_read(u8 reg, u16 slave); |
| 59 | int prcmu_i2c_write(u8 reg, u16 slave, u8 reg_data); |
| John Rigby | 25a3362 | 2011-04-19 10:42:42 +0000 | [diff] [blame] | 60 | |
| Mathieu J. Poirier | 6579898 | 2012-07-31 08:59:25 +0000 | [diff] [blame] | 61 | void u8500_prcmu_enable(u32 *reg); |
| 62 | void db8500_prcmu_init(void); |
| 63 | |
| John Rigby | 25a3362 | 2011-04-19 10:42:42 +0000 | [diff] [blame] | 64 | #endif /* __MACH_PRCMU_FW_V1_H */ |