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Gregory CLEMENTb622f8f2018-12-14 16:16:49 +01001// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2018 Microsemi Corporation
4 */
5
6/ {
7 #address-cells = <1>;
8 #size-cells = <1>;
9 compatible = "mscc,ocelot";
10
11 cpus {
12 #address-cells = <1>;
13 #size-cells = <0>;
14
15 cpu@0 {
16 compatible = "mips,mips24KEc";
17 device_type = "cpu";
18 clocks = <&cpu_clk>;
19 reg = <0>;
20 };
21 };
22
23 aliases {
24 serial0 = &uart0;
25 };
26
27 cpuintc: interrupt-controller@0 {
28 #address-cells = <0>;
29 #interrupt-cells = <1>;
30 interrupt-controller;
31 compatible = "mti,cpu-interrupt-controller";
32 };
33
34 cpu_clk: cpu-clock {
35 compatible = "fixed-clock";
36 #clock-cells = <0>;
37 clock-frequency = <500000000>;
38 };
39
Lars Povlsen713be902019-01-02 09:52:25 +010040 sys_clk: sys-clk {
41 compatible = "fixed-clock";
42 #clock-cells = <0>;
43 clock-frequency = <250000000>;
44 };
45
Gregory CLEMENTb622f8f2018-12-14 16:16:49 +010046 ahb_clk: ahb-clk {
47 compatible = "fixed-clock";
48 #clock-cells = <0>;
49 clock-frequency = <250000000>;
50 };
51
52 ahb {
53 compatible = "simple-bus";
54 #address-cells = <1>;
55 #size-cells = <1>;
56 ranges = <0 0x70000000 0x2000000>;
57
58 interrupt-parent = <&intc>;
59
60 cpu_ctrl: syscon@0 {
61 compatible = "mscc,ocelot-cpu-syscon", "syscon";
62 reg = <0x0 0x2c>;
63 };
64
65 intc: interrupt-controller@70 {
66 compatible = "mscc,ocelot-icpu-intr";
67 reg = <0x70 0x70>;
68 #interrupt-cells = <1>;
69 interrupt-controller;
70 interrupt-parent = <&cpuintc>;
71 interrupts = <2>;
72 };
73
74 uart0: serial@100000 {
75 pinctrl-0 = <&uart_pins>;
76 pinctrl-names = "default";
77 compatible = "ns16550a";
78 reg = <0x100000 0x20>;
79 interrupts = <6>;
80 clocks = <&ahb_clk>;
81 reg-io-width = <4>;
82 reg-shift = <2>;
83
84 status = "disabled";
85 };
86
87 uart2: serial@100800 {
88 pinctrl-0 = <&uart2_pins>;
89 pinctrl-names = "default";
90 compatible = "ns16550a";
91 reg = <0x100800 0x20>;
92 interrupts = <7>;
93 clocks = <&ahb_clk>;
94 reg-io-width = <4>;
95 reg-shift = <2>;
96
97 status = "disabled";
98 };
99
100 spi0: spi-master@101000 {
101 #address-cells = <1>;
102 #size-cells = <0>;
103 compatible = "snps,dw-apb-ssi";
104 reg = <0x101000 0x40>;
105 num-chipselect = <4>;
106 bus-num = <0>;
107 reg-io-width = <4>;
108 reg-shift = <2>;
109 spi-max-frequency = <18000000>; /* input clock */
110 clocks = <&ahb_clk>;
111
112 status = "disabled";
113 };
114
Gregory CLEMENT7d09cdc2019-01-17 17:07:12 +0100115 switch@1010000 {
116 pinctrl-0 = <&miim1_pins>;
117 pinctrl-names = "default";
118
119 compatible = "mscc,vsc7514-switch";
120 reg = <0x1010000 0x10000>, /* VTSS_TO_SYS */
121 <0x1030000 0x10000>, /* VTSS_TO_REW */
122 <0x1080000 0x100>, /* VTSS_TO_DEVCPU_QS */
123 <0x10d0000 0x10000>, /* VTSS_TO_HSIO */
124 <0x11e0000 0x100>, /* VTSS_TO_DEV_0 */
125 <0x11f0000 0x100>, /* VTSS_TO_DEV_1 */
126 <0x1200000 0x100>, /* VTSS_TO_DEV_2 */
127 <0x1210000 0x100>, /* VTSS_TO_DEV_3 */
128 <0x1220000 0x100>, /* VTSS_TO_DEV_4 */
129 <0x1230000 0x100>, /* VTSS_TO_DEV_5 */
130 <0x1240000 0x100>, /* VTSS_TO_DEV_6 */
131 <0x1250000 0x100>, /* VTSS_TO_DEV_7 */
132 <0x1260000 0x100>, /* VTSS_TO_DEV_8 */
133 <0x1270000 0x100>, /* NA */
134 <0x1280000 0x100>, /* NA */
135 <0x1800000 0x80000>, /* VTSS_TO_QSYS */
136 <0x1880000 0x10000>; /* VTSS_TO_ANA */
137 reg-names = "sys", "rew", "qs", "hsio", "port0",
138 "port1", "port2", "port3", "port4", "port5",
139 "port6", "port7", "port8", "port9",
140 "port10", "qsys", "ana";
141 interrupts = <21 22>;
142 interrupt-names = "xtr", "inj";
143 status = "okay";
144
145 ethernet-ports {
146 #address-cells = <1>;
147 #size-cells = <0>;
148
149 port0: port@0 {
150 reg = <0>;
151 };
152 port1: port@1 {
153 reg = <1>;
154 };
155 port2: port@2 {
156 reg = <2>;
157 };
158 port3: port@3 {
159 reg = <3>;
160 };
161 port4: port@4 {
162 reg = <4>;
163 };
164 port5: port@5 {
165 reg = <5>;
166 };
167 port6: port@6 {
168 reg = <6>;
169 };
170 port7: port@7 {
171 reg = <7>;
172 };
173 port8: port@8 {
174 reg = <8>;
175 };
176 port9: port@9 {
177 reg = <9>;
178 };
179 port10: port@10 {
180 reg = <10>;
181 };
182 };
183 };
184
185 mdio0: mdio@107009c {
186 #address-cells = <1>;
187 #size-cells = <0>;
188 compatible = "mscc,ocelot-miim";
189 reg = <0x107009c 0x24>, <0x10700f0 0x8>;
190 interrupts = <14>;
191 status = "disabled";
192
193 phy0: ethernet-phy@0 {
194 reg = <0>;
195 };
196 phy1: ethernet-phy@1 {
197 reg = <1>;
198 };
199 phy2: ethernet-phy@2 {
200 reg = <2>;
201 };
202 phy3: ethernet-phy@3 {
203 reg = <3>;
204 };
205 };
206
Gregory CLEMENTb622f8f2018-12-14 16:16:49 +0100207 reset@1070008 {
208 compatible = "mscc,ocelot-chip-reset";
209 reg = <0x1070008 0x4>;
210 };
211
212 gpio: pinctrl@1070034 {
213 compatible = "mscc,ocelot-pinctrl";
214 reg = <0x1070034 0x68>;
215 gpio-controller;
216 #gpio-cells = <2>;
217 gpio-ranges = <&gpio 0 0 22>;
218
Lars Povlsen713be902019-01-02 09:52:25 +0100219 sgpio_pins: sgpio-pins {
220 pins = "GPIO_0", "GPIO_1", "GPIO_2", "GPIO_3";
221 function = "sg0";
222 };
223
Gregory CLEMENTb622f8f2018-12-14 16:16:49 +0100224 uart_pins: uart-pins {
225 pins = "GPIO_6", "GPIO_7";
226 function = "uart";
227 };
228
229 uart2_pins: uart2-pins {
230 pins = "GPIO_12", "GPIO_13";
231 function = "uart2";
232 };
233
234 spi_cs1_pin: spi-cs1-pin {
235 pins = "GPIO_8";
236 function = "si";
237 };
238
Gregory CLEMENT7d09cdc2019-01-17 17:07:12 +0100239 miim1_pins: miim1-pins {
240 pins = "GPIO_14", "GPIO_15";
241 function = "miim1";
242 };
243
Gregory CLEMENTb622f8f2018-12-14 16:16:49 +0100244 spi_cs2_pin: spi-cs2-pin {
245 pins = "GPIO_9";
246 function = "si";
247 };
248
249 spi_cs3_pin: spi-cs3-pin {
250 pins = "GPIO_16";
251 function = "si";
252 };
253
254 spi_cs4_pin: spi-cs4-pin {
255 pins = "GPIO_17";
256 function = "si";
257 };
258 };
Lars Povlsen713be902019-01-02 09:52:25 +0100259
260 sgpio: gpio@10700f8 {
261 compatible = "mscc,ocelot-sgpio";
262 status = "disabled";
263 clocks = <&sys_clk>;
264 pinctrl-0 = <&sgpio_pins>;
265 pinctrl-names = "default";
266 reg = <0x10700f8 0x100>;
267 gpio-controller;
268 #gpio-cells = <2>;
269 gpio-ranges = <&sgpio 0 0 64>;
270 };
Gregory CLEMENTb622f8f2018-12-14 16:16:49 +0100271 };
272};