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git01.mediatek.com / filogic / uboot / c6f15de617303cef1e87a2658f21a696099dc5ce / . / arch / sandbox / dts / test.dts
blob: 5fa951ad4b6e971353ce8765ecad27083b4ce5c6 [file] [log] [blame]
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]1/dts-v1/;
2
3/ {
4 model = "sandbox";
5 compatible = "sandbox";
6 #address-cells = <1>;
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]7 #size-cells = <1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]8
Simon Glassfef72b72014-07-23 06:55:03 -0600[diff] [blame]9 aliases {
10 console = &uart0;
Simon Glass5b968632015-05-22 15:42:15 -0600[diff] [blame]11 eth0 = "/eth@10002000";
Bin Meng04a11cb2015-08-27 22:25:53 -0700[diff] [blame]12 eth3 = &eth_3;
Simon Glass5b968632015-05-22 15:42:15 -0600[diff] [blame]13 eth5 = &eth_5;
Simon Glass5620cf82018-10-01 12:22:40 -0600[diff] [blame]14 gpio1 = &gpio_a;
15 gpio2 = &gpio_b;
Simon Glass0ccb0972015-01-25 08:27:05 -0700[diff] [blame]16 i2c0 = "/i2c@0";
Simon Glasse4fef742017-04-23 20:02:07 -0600[diff] [blame]17 mmc0 = "/mmc0";
18 mmc1 = "/mmc1";
Bin Meng408e5902018-08-03 01:14:41 -0700[diff] [blame]19 pci0 = &pci0;
20 pci1 = &pci1;
Bin Meng510dddb2018-08-03 01:14:50 -0700[diff] [blame]21 pci2 = &pci2;
Nishanth Menonedf85812015-09-17 15:42:41 -0500[diff] [blame]22 remoteproc1 = &rproc_1;
23 remoteproc2 = &rproc_2;
Simon Glass336b2952015-05-22 15:42:17 -0600[diff] [blame]24 rtc0 = &rtc_0;
25 rtc1 = &rtc_1;
Simon Glass5b968632015-05-22 15:42:15 -0600[diff] [blame]26 spi0 = "/spi@0";
Przemyslaw Marczak3dbb55e2015-05-13 13:38:34 +0200[diff] [blame]27 testfdt6 = "/e-test";
Simon Glass0ccb0972015-01-25 08:27:05 -0700[diff] [blame]28 testbus3 = "/some-bus";
29 testfdt0 = "/some-bus/c-test@0";
30 testfdt1 = "/some-bus/c-test@1";
31 testfdt3 = "/b-test";
32 testfdt5 = "/some-bus/c-test@5";
33 testfdt8 = "/a-test";
Eugeniu Rosca5ba71e52018-05-19 14:13:55 +0200[diff] [blame]34 fdt-dummy0 = "/translation-test@8000/dev@0,0";
35 fdt-dummy1 = "/translation-test@8000/dev@1,100";
36 fdt-dummy2 = "/translation-test@8000/dev@2,200";
37 fdt-dummy3 = "/translation-test@8000/noxlatebus@3,300/dev@42";
Simon Glass31680482015-03-25 12:23:05 -0600[diff] [blame]38 usb0 = &usb_0;
39 usb1 = &usb_1;
40 usb2 = &usb_2;
Mario Six95922152018-08-09 14:51:19 +0200[diff] [blame]41 axi0 = &axi;
Mario Six02ad6fb2018-09-27 09:19:31 +0200[diff] [blame]42 osd0 = "/osd";
Simon Glassfef72b72014-07-23 06:55:03 -0600[diff] [blame]43 };
44
Simon Glassed96cde2018-12-10 10:37:33 -0700[diff] [blame]45 audio: audio-codec {
46 compatible = "sandbox,audio-codec";
47 #sound-dai-cells = <1>;
48 };
49
Simon Glassc953aaf2018-12-10 10:37:34 -0700[diff] [blame]50 cros_ec: cros-ec {
Simon Glass699c9ca2018-10-01 12:22:08 -0600[diff] [blame]51 reg = <0 0>;
52 compatible = "google,cros-ec-sandbox";
53
54 /*
55 * This describes the flash memory within the EC. Note
56 * that the STM32L flash erases to 0, not 0xff.
57 */
58 flash {
59 image-pos = <0x08000000>;
60 size = <0x20000>;
61 erase-value = <0>;
62
63 /* Information for sandbox */
64 ro {
65 image-pos = <0>;
66 size = <0xf000>;
67 };
68 wp-ro {
69 image-pos = <0xf000>;
70 size = <0x1000>;
71 };
72 rw {
73 image-pos = <0x10000>;
74 size = <0x10000>;
75 };
76 };
77 };
78
Yannick Fertré9712c822019-10-07 15:29:05 +0200[diff] [blame]79 dsi_host: dsi_host {
80 compatible = "sandbox,dsi-host";
81 };
82
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]83 a-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]84 reg = <0 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]85 compatible = "denx,u-boot-fdt-test";
Simon Glassa7bb08a2014-07-23 06:54:57 -0600[diff] [blame]86 ping-expect = <0>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]87 ping-add = <0>;
Simon Glassfef72b72014-07-23 06:55:03 -0600[diff] [blame]88 u-boot,dm-pre-reloc;
Simon Glass16e10402015-01-05 20:05:29 -0700[diff] [blame]89 test-gpios = <&gpio_a 1>, <&gpio_a 4>, <&gpio_b 5 0 3 2 1>,
90 <0>, <&gpio_a 12>;
91 test2-gpios = <&gpio_a 1>, <&gpio_a 4>, <&gpio_b 6 1 3 2 1>,
92 <&gpio_b 7 2 3 2 1>, <&gpio_b 8 4 3 2 1>,
93 <&gpio_b 9 0xc 3 2 1>;
Simon Glass6df01f92018-12-10 10:37:37 -0700[diff] [blame]94 int-value = <1234>;
95 uint-value = <(-1234)>;
Simon Glass515dcff2020-02-06 09:55:00 -0700[diff] [blame]96 interrupts-extended = <&irq 3 0>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]97 };
98
99 junk {
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]100 reg = <1 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]101 compatible = "not,compatible";
102 };
103
104 no-compatible {
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]105 reg = <2 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]106 };
107
Simon Glass5620cf82018-10-01 12:22:40 -0600[diff] [blame]108 backlight: backlight {
109 compatible = "pwm-backlight";
110 enable-gpios = <&gpio_a 1>;
111 power-supply = <&ldo_1>;
112 pwms = <&pwm 0 1000>;
113 default-brightness-level = <5>;
114 brightness-levels = <0 16 32 64 128 170 202 234 255>;
115 };
116
Jean-Jacques Hiblote83a31b2018-08-09 16:17:46 +0200[diff] [blame]117 bind-test {
118 bind-test-child1 {
119 compatible = "sandbox,phy";
120 #phy-cells = <1>;
121 };
122
123 bind-test-child2 {
124 compatible = "simple-bus";
125 };
126 };
127
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]128 b-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]129 reg = <3 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]130 compatible = "denx,u-boot-fdt-test";
Simon Glassa7bb08a2014-07-23 06:54:57 -0600[diff] [blame]131 ping-expect = <3>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]132 ping-add = <3>;
133 };
134
Jean-Jacques Hiblot7e9db022017-04-24 11:51:28 +0200[diff] [blame]135 phy_provider0: gen_phy@0 {
136 compatible = "sandbox,phy";
137 #phy-cells = <1>;
138 };
139
140 phy_provider1: gen_phy@1 {
141 compatible = "sandbox,phy";
142 #phy-cells = <0>;
143 broken;
144 };
145
146 gen_phy_user: gen_phy_user {
147 compatible = "simple-bus";
148 phys = <&phy_provider0 0>, <&phy_provider0 1>, <&phy_provider1>;
149 phy-names = "phy1", "phy2", "phy3";
150 };
151
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]152 some-bus {
153 #address-cells = <1>;
154 #size-cells = <0>;
Simon Glass40717422014-07-23 06:55:18 -0600[diff] [blame]155 compatible = "denx,u-boot-test-bus";
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]156 reg = <3 1>;
Simon Glassa7bb08a2014-07-23 06:54:57 -0600[diff] [blame]157 ping-expect = <4>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]158 ping-add = <4>;
Simon Glass40717422014-07-23 06:55:18 -0600[diff] [blame]159 c-test@5 {
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]160 compatible = "denx,u-boot-fdt-test";
161 reg = <5>;
Simon Glass40717422014-07-23 06:55:18 -0600[diff] [blame]162 ping-expect = <5>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]163 ping-add = <5>;
164 };
Simon Glass40717422014-07-23 06:55:18 -0600[diff] [blame]165 c-test@0 {
166 compatible = "denx,u-boot-fdt-test";
167 reg = <0>;
168 ping-expect = <6>;
169 ping-add = <6>;
170 };
171 c-test@1 {
172 compatible = "denx,u-boot-fdt-test";
173 reg = <1>;
174 ping-expect = <7>;
175 ping-add = <7>;
176 };
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]177 };
178
179 d-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]180 reg = <3 1>;
Simon Glassdb6f0202014-07-23 06:55:12 -0600[diff] [blame]181 ping-expect = <6>;
182 ping-add = <6>;
183 compatible = "google,another-fdt-test";
184 };
185
186 e-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]187 reg = <3 1>;
Simon Glassa7bb08a2014-07-23 06:54:57 -0600[diff] [blame]188 ping-expect = <6>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]189 ping-add = <6>;
190 compatible = "google,another-fdt-test";
191 };
192
Simon Glass0ccb0972015-01-25 08:27:05 -0700[diff] [blame]193 f-test {
194 compatible = "denx,u-boot-fdt-test";
195 };
196
197 g-test {
198 compatible = "denx,u-boot-fdt-test";
199 };
200
Bin Mengd9d24782018-10-10 22:07:01 -0700[diff] [blame]201 h-test {
202 compatible = "denx,u-boot-fdt-test1";
203 };
204
Simon Glass204675c2019-12-29 21:19:25 -0700[diff] [blame]205 devres-test {
206 compatible = "denx,u-boot-devres-test";
207 };
208
Simon Glass2d67fdf2020-04-08 16:57:34 -0600[diff] [blame]209 acpi-test {
210 compatible = "denx,u-boot-acpi-test";
211 };
212
Patrice Chotard9cc2d142017-09-04 14:55:57 +0200[diff] [blame]213 clocks {
214 clk_fixed: clk-fixed {
215 compatible = "fixed-clock";
216 #clock-cells = <0>;
217 clock-frequency = <1234>;
218 };
Anup Patel8d28c3c2019-02-25 08:14:55 +0000[diff] [blame]219
220 clk_fixed_factor: clk-fixed-factor {
221 compatible = "fixed-factor-clock";
222 #clock-cells = <0>;
223 clock-div = <3>;
224 clock-mult = <2>;
225 clocks = <&clk_fixed>;
226 };
Lukasz Majewskiccafcdd2019-06-24 15:50:47 +0200[diff] [blame]227
228 osc {
229 compatible = "fixed-clock";
230 #clock-cells = <0>;
231 clock-frequency = <20000000>;
232 };
Stephen Warrena9622432016-06-17 09:44:00 -0600[diff] [blame]233 };
234
235 clk_sandbox: clk-sbox {
Simon Glass8cc4d822015-07-06 12:54:24 -0600[diff] [blame]236 compatible = "sandbox,clk";
Stephen Warrena9622432016-06-17 09:44:00 -0600[diff] [blame]237 #clock-cells = <1>;
Jean-Jacques Hiblotc1e9c942019-10-22 14:00:07 +0200[diff] [blame]238 assigned-clocks = <&clk_sandbox 3>;
239 assigned-clock-rates = <321>;
Stephen Warrena9622432016-06-17 09:44:00 -0600[diff] [blame]240 };
241
242 clk-test {
243 compatible = "sandbox,clk-test";
244 clocks = <&clk_fixed>,
245 <&clk_sandbox 1>,
Jean-Jacques Hiblot98e84182019-10-22 14:00:05 +0200[diff] [blame]246 <&clk_sandbox 0>,
247 <&clk_sandbox 3>,
248 <&clk_sandbox 2>;
249 clock-names = "fixed", "i2c", "spi", "uart2", "uart1";
Simon Glass8cc4d822015-07-06 12:54:24 -0600[diff] [blame]250 };
251
Lukasz Majewski8c0709b2019-06-24 15:50:50 +0200[diff] [blame]252 ccf: clk-ccf {
253 compatible = "sandbox,clk-ccf";
254 };
255
Simon Glass5b968632015-05-22 15:42:15 -0600[diff] [blame]256 eth@10002000 {
257 compatible = "sandbox,eth";
258 reg = <0x10002000 0x1000>;
Joe Hershberger76f3c102018-07-02 14:47:45 -0500[diff] [blame]259 fake-host-hwaddr = [00 00 66 44 22 00];
Simon Glass5b968632015-05-22 15:42:15 -0600[diff] [blame]260 };
261
262 eth_5: eth@10003000 {
263 compatible = "sandbox,eth";
264 reg = <0x10003000 0x1000>;
Joe Hershberger76f3c102018-07-02 14:47:45 -0500[diff] [blame]265 fake-host-hwaddr = [00 00 66 44 22 11];
Simon Glass5b968632015-05-22 15:42:15 -0600[diff] [blame]266 };
267
Bin Meng04a11cb2015-08-27 22:25:53 -0700[diff] [blame]268 eth_3: sbe5 {
269 compatible = "sandbox,eth";
270 reg = <0x10005000 0x1000>;
Joe Hershberger76f3c102018-07-02 14:47:45 -0500[diff] [blame]271 fake-host-hwaddr = [00 00 66 44 22 33];
Bin Meng04a11cb2015-08-27 22:25:53 -0700[diff] [blame]272 };
273
Simon Glass5b968632015-05-22 15:42:15 -0600[diff] [blame]274 eth@10004000 {
275 compatible = "sandbox,eth";
276 reg = <0x10004000 0x1000>;
Joe Hershberger76f3c102018-07-02 14:47:45 -0500[diff] [blame]277 fake-host-hwaddr = [00 00 66 44 22 22];
Simon Glass5b968632015-05-22 15:42:15 -0600[diff] [blame]278 };
279
Rajan Vajab3b2ddb2018-09-19 03:43:46 -0700[diff] [blame]280 firmware {
281 sandbox_firmware: sandbox-firmware {
282 compatible = "sandbox,firmware";
283 };
284 };
285
Simon Glass25348a42014-10-13 23:42:11 -0600[diff] [blame]286 gpio_a: base-gpios {
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]287 compatible = "sandbox,gpio";
Simon Glass16e10402015-01-05 20:05:29 -0700[diff] [blame]288 gpio-controller;
289 #gpio-cells = <1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]290 gpio-bank-name = "a";
Simon Glass9e7ab232018-02-03 10:36:59 -0700[diff] [blame]291 sandbox,gpio-count = <20>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]292 };
293
Simon Glass16e10402015-01-05 20:05:29 -0700[diff] [blame]294 gpio_b: extra-gpios {
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]295 compatible = "sandbox,gpio";
Simon Glass16e10402015-01-05 20:05:29 -0700[diff] [blame]296 gpio-controller;
297 #gpio-cells = <5>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]298 gpio-bank-name = "b";
Simon Glass9e7ab232018-02-03 10:36:59 -0700[diff] [blame]299 sandbox,gpio-count = <10>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]300 };
Simon Glass25348a42014-10-13 23:42:11 -0600[diff] [blame]301
Simon Glass7df766e2014-12-10 08:55:55 -0700[diff] [blame]302 i2c@0 {
303 #address-cells = <1>;
304 #size-cells = <0>;
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]305 reg = <0 1>;
Simon Glass7df766e2014-12-10 08:55:55 -0700[diff] [blame]306 compatible = "sandbox,i2c";
307 clock-frequency = <100000>;
308 eeprom@2c {
309 reg = <0x2c>;
310 compatible = "i2c-eeprom";
Simon Glass17b56f62018-11-18 08:14:34 -0700[diff] [blame]311 sandbox,emul = <&emul_eeprom>;
Simon Glass7df766e2014-12-10 08:55:55 -0700[diff] [blame]312 };
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200[diff] [blame]313
Simon Glass336b2952015-05-22 15:42:17 -0600[diff] [blame]314 rtc_0: rtc@43 {
315 reg = <0x43>;
316 compatible = "sandbox-rtc";
Simon Glass17b56f62018-11-18 08:14:34 -0700[diff] [blame]317 sandbox,emul = <&emul0>;
Simon Glass336b2952015-05-22 15:42:17 -0600[diff] [blame]318 };
319
320 rtc_1: rtc@61 {
321 reg = <0x61>;
322 compatible = "sandbox-rtc";
Simon Glass17b56f62018-11-18 08:14:34 -0700[diff] [blame]323 sandbox,emul = <&emul1>;
324 };
325
326 i2c_emul: emul {
327 reg = <0xff>;
328 compatible = "sandbox,i2c-emul-parent";
329 emul_eeprom: emul-eeprom {
330 compatible = "sandbox,i2c-eeprom";
331 sandbox,filename = "i2c.bin";
332 sandbox,size = <256>;
333 };
334 emul0: emul0 {
335 compatible = "sandbox,i2c-rtc";
336 };
337 emul1: emull {
Simon Glass336b2952015-05-22 15:42:17 -0600[diff] [blame]338 compatible = "sandbox,i2c-rtc";
339 };
340 };
341
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200[diff] [blame]342 sandbox_pmic: sandbox_pmic {
343 reg = <0x40>;
Simon Glass17b56f62018-11-18 08:14:34 -0700[diff] [blame]344 sandbox,emul = <&emul_pmic0>;
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200[diff] [blame]345 };
Lukasz Majewskia4d82972018-05-15 16:26:40 +0200[diff] [blame]346
347 mc34708: pmic@41 {
348 reg = <0x41>;
Simon Glass17b56f62018-11-18 08:14:34 -0700[diff] [blame]349 sandbox,emul = <&emul_pmic1>;
Lukasz Majewskia4d82972018-05-15 16:26:40 +0200[diff] [blame]350 };
Simon Glass7df766e2014-12-10 08:55:55 -0700[diff] [blame]351 };
352
Philipp Tomsich1fc53302018-12-14 21:14:29 +0100[diff] [blame]353 bootcount@0 {
354 compatible = "u-boot,bootcount-rtc";
355 rtc = <&rtc_1>;
356 offset = <0x13>;
357 };
358
Przemyslaw Marczak1bc7f232015-10-27 13:08:06 +0100[diff] [blame]359 adc@0 {
360 compatible = "sandbox,adc";
361 vdd-supply = <&buck2>;
362 vss-microvolts = <0>;
363 };
364
Simon Glass515dcff2020-02-06 09:55:00 -0700[diff] [blame]365 irq: irq {
Simon Glass54028bc2019-12-06 21:41:59 -0700[diff] [blame]366 compatible = "sandbox,irq";
Simon Glass515dcff2020-02-06 09:55:00 -0700[diff] [blame]367 interrupt-controller;
368 #interrupt-cells = <2>;
Simon Glass54028bc2019-12-06 21:41:59 -0700[diff] [blame]369 };
370
Simon Glass90b6fef2016-01-18 19:52:26 -0700[diff] [blame]371 lcd {
372 u-boot,dm-pre-reloc;
373 compatible = "sandbox,lcd-sdl";
374 xres = <1366>;
375 yres = <768>;
376 };
377
Simon Glassd783eb32015-07-06 12:54:34 -0600[diff] [blame]378 leds {
379 compatible = "gpio-leds";
380
381 iracibble {
382 gpios = <&gpio_a 1 0>;
383 label = "sandbox:red";
384 };
385
386 martinet {
387 gpios = <&gpio_a 2 0>;
388 label = "sandbox:green";
389 };
Patrick Bruennb58adfe2018-04-11 11:16:29 +0200[diff] [blame]390
391 default_on {
392 gpios = <&gpio_a 5 0>;
393 label = "sandbox:default_on";
394 default-state = "on";
395 };
396
397 default_off {
398 gpios = <&gpio_a 6 0>;
399 label = "sandbox:default_off";
400 default-state = "off";
401 };
Simon Glassd783eb32015-07-06 12:54:34 -0600[diff] [blame]402 };
403
Stephen Warren62f2c902016-05-16 17:41:37 -0600[diff] [blame]404 mbox: mbox {
405 compatible = "sandbox,mbox";
406 #mbox-cells = <1>;
407 };
408
409 mbox-test {
410 compatible = "sandbox,mbox-test";
411 mboxes = <&mbox 100>, <&mbox 1>;
412 mbox-names = "other", "test";
413 };
414
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900[diff] [blame]415 cpus {
416 cpu-test1 {
417 compatible = "sandbox,cpu_sandbox";
418 u-boot,dm-pre-reloc;
419 };
Mario Sixdea5df72018-08-06 10:23:44 +0200[diff] [blame]420
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900[diff] [blame]421 cpu-test2 {
422 compatible = "sandbox,cpu_sandbox";
423 u-boot,dm-pre-reloc;
424 };
Mario Sixdea5df72018-08-06 10:23:44 +0200[diff] [blame]425
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900[diff] [blame]426 cpu-test3 {
427 compatible = "sandbox,cpu_sandbox";
428 u-boot,dm-pre-reloc;
429 };
Mario Sixdea5df72018-08-06 10:23:44 +0200[diff] [blame]430 };
431
Simon Glassc953aaf2018-12-10 10:37:34 -0700[diff] [blame]432 i2s: i2s {
433 compatible = "sandbox,i2s";
434 #sound-dai-cells = <1>;
Simon Glass4d5814c2019-02-16 20:24:56 -0700[diff] [blame]435 sandbox,silent; /* Don't emit sounds while testing */
Simon Glassc953aaf2018-12-10 10:37:34 -0700[diff] [blame]436 };
437
Jean-Jacques Hiblotdb97c7f2019-07-05 09:33:57 +0200[diff] [blame]438 nop-test_0 {
439 compatible = "sandbox,nop_sandbox1";
440 nop-test_1 {
441 compatible = "sandbox,nop_sandbox2";
442 bind = "True";
443 };
444 nop-test_2 {
445 compatible = "sandbox,nop_sandbox2";
446 bind = "False";
447 };
448 };
449
Mario Sixa8ce0ee2018-07-31 14:24:14 +0200[diff] [blame]450 misc-test {
451 compatible = "sandbox,misc_sandbox";
452 };
453
Simon Glasse4fef742017-04-23 20:02:07 -0600[diff] [blame]454 mmc2 {
455 compatible = "sandbox,mmc";
456 };
457
458 mmc1 {
459 compatible = "sandbox,mmc";
460 };
461
462 mmc0 {
Simon Glassd3e58e42015-07-06 12:54:32 -0600[diff] [blame]463 compatible = "sandbox,mmc";
464 };
465
Simon Glass53a68b32019-02-16 20:24:50 -0700[diff] [blame]466 pch {
467 compatible = "sandbox,pch";
468 };
469
Bin Meng408e5902018-08-03 01:14:41 -0700[diff] [blame]470 pci0: pci-controller0 {
Simon Glass3a6eae62015-03-05 12:25:34 -0700[diff] [blame]471 compatible = "sandbox,pci";
472 device_type = "pci";
473 #address-cells = <3>;
474 #size-cells = <2>;
Simon Glass35464f72019-09-25 08:56:08 -0600[diff] [blame]475 ranges = <0x02000000 0 0x10000000 0x10000000 0 0x2000000
Simon Glass3a6eae62015-03-05 12:25:34 -0700[diff] [blame]476 0x01000000 0 0x20000000 0x20000000 0 0x2000>;
Bin Mengcbf071b2018-08-03 01:14:39 -0700[diff] [blame]477 pci@0,0 {
478 compatible = "pci-generic";
479 reg = <0x0000 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -0600[diff] [blame]480 sandbox,emul = <&swap_case_emul0_0>;
Bin Mengcbf071b2018-08-03 01:14:39 -0700[diff] [blame]481 };
Alex Margineanf1274432019-06-07 11:24:24 +0300[diff] [blame]482 pci@1,0 {
483 compatible = "pci-generic";
Simon Glass23b27592019-09-15 12:08:58 -0600[diff] [blame]484 /* reg 0 is at 0x14, using FDT_PCI_SPACE_MEM32 */
485 reg = <0x02000814 0 0 0 0
486 0x01000810 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -0600[diff] [blame]487 sandbox,emul = <&swap_case_emul0_1>;
Alex Margineanf1274432019-06-07 11:24:24 +0300[diff] [blame]488 };
Simon Glass937bb472019-12-06 21:41:57 -0700[diff] [blame]489 p2sb-pci@2,0 {
490 compatible = "sandbox,p2sb";
491 reg = <0x02001010 0 0 0 0>;
492 sandbox,emul = <&p2sb_emul>;
493
494 adder {
495 intel,p2sb-port-id = <3>;
496 compatible = "sandbox,adder";
497 };
498 };
Simon Glass8c501022019-12-06 21:41:54 -0700[diff] [blame]499 pci@1e,0 {
500 compatible = "sandbox,pmc";
501 reg = <0xf000 0 0 0 0>;
502 sandbox,emul = <&pmc_emul1e>;
503 acpi-base = <0x400>;
504 gpe0-dwx-mask = <0xf>;
505 gpe0-dwx-shift-base = <4>;
506 gpe0-dw = <6 7 9>;
507 gpe0-sts = <0x20>;
508 gpe0-en = <0x30>;
509 };
Simon Glass3a6eae62015-03-05 12:25:34 -0700[diff] [blame]510 pci@1f,0 {
511 compatible = "pci-generic";
Simon Glass23b27592019-09-15 12:08:58 -0600[diff] [blame]512 /* reg 0 is at 0x10, using FDT_PCI_SPACE_IO */
513 reg = <0x0100f810 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -0600[diff] [blame]514 sandbox,emul = <&swap_case_emul0_1f>;
Simon Glass3a6eae62015-03-05 12:25:34 -0700[diff] [blame]515 };
516 };
517
Simon Glassb98ba4c2019-09-25 08:56:10 -0600[diff] [blame]518 pci-emul0 {
519 compatible = "sandbox,pci-emul-parent";
520 swap_case_emul0_0: emul0@0,0 {
521 compatible = "sandbox,swap-case";
522 };
523 swap_case_emul0_1: emul0@1,0 {
524 compatible = "sandbox,swap-case";
525 use-ea;
526 };
527 swap_case_emul0_1f: emul0@1f,0 {
528 compatible = "sandbox,swap-case";
529 };
Simon Glass937bb472019-12-06 21:41:57 -0700[diff] [blame]530 p2sb_emul: emul@2,0 {
531 compatible = "sandbox,p2sb-emul";
532 };
Simon Glass8c501022019-12-06 21:41:54 -0700[diff] [blame]533 pmc_emul1e: emul@1e,0 {
534 compatible = "sandbox,pmc-emul";
535 };
Simon Glassb98ba4c2019-09-25 08:56:10 -0600[diff] [blame]536 };
537
Bin Meng408e5902018-08-03 01:14:41 -0700[diff] [blame]538 pci1: pci-controller1 {
539 compatible = "sandbox,pci";
540 device_type = "pci";
541 #address-cells = <3>;
542 #size-cells = <2>;
543 ranges = <0x02000000 0 0x30000000 0x30000000 0 0x2000
544 0x01000000 0 0x40000000 0x40000000 0 0x2000>;
Bin Meng5fed5362018-08-03 01:14:47 -0700[diff] [blame]545 sandbox,dev-info = <0x08 0x00 0x1234 0x5678
Marek Vasute5733222018-10-10 21:27:08 +0200[diff] [blame]546 0x0c 0x00 0x1234 0x5678
547 0x10 0x00 0x1234 0x5678>;
548 pci@10,0 {
549 reg = <0x8000 0 0 0 0>;
550 };
Bin Meng408e5902018-08-03 01:14:41 -0700[diff] [blame]551 };
552
Bin Meng510dddb2018-08-03 01:14:50 -0700[diff] [blame]553 pci2: pci-controller2 {
554 compatible = "sandbox,pci";
555 device_type = "pci";
556 #address-cells = <3>;
557 #size-cells = <2>;
558 ranges = <0x02000000 0 0x50000000 0x50000000 0 0x2000
559 0x01000000 0 0x60000000 0x60000000 0 0x2000>;
560 sandbox,dev-info = <0x08 0x00 0x1234 0x5678>;
561 pci@1f,0 {
562 compatible = "pci-generic";
563 reg = <0xf800 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -0600[diff] [blame]564 sandbox,emul = <&swap_case_emul2_1f>;
565 };
566 };
567
568 pci-emul2 {
569 compatible = "sandbox,pci-emul-parent";
570 swap_case_emul2_1f: emul2@1f,0 {
571 compatible = "sandbox,swap-case";
Bin Meng510dddb2018-08-03 01:14:50 -0700[diff] [blame]572 };
573 };
574
Ramon Friedc64f19b2019-04-27 11:15:23 +0300[diff] [blame]575 pci_ep: pci_ep {
576 compatible = "sandbox,pci_ep";
577 };
578
Simon Glass9c433fe2017-04-23 20:10:44 -0600[diff] [blame]579 probing {
580 compatible = "simple-bus";
581 test1 {
582 compatible = "denx,u-boot-probe-test";
583 };
584
585 test2 {
586 compatible = "denx,u-boot-probe-test";
587 };
588
589 test3 {
590 compatible = "denx,u-boot-probe-test";
591 };
592
593 test4 {
594 compatible = "denx,u-boot-probe-test";
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +0100[diff] [blame]595 first-syscon = <&syscon0>;
596 second-sys-ctrl = <&another_system_controller>;
Patrick Delaunayee010432019-03-07 09:57:13 +0100[diff] [blame]597 third-syscon = <&syscon2>;
Simon Glass9c433fe2017-04-23 20:10:44 -0600[diff] [blame]598 };
599 };
600
Stephen Warren92c67fa2016-07-13 13:45:31 -0600[diff] [blame]601 pwrdom: power-domain {
602 compatible = "sandbox,power-domain";
603 #power-domain-cells = <1>;
604 };
605
606 power-domain-test {
607 compatible = "sandbox,power-domain-test";
608 power-domains = <&pwrdom 2>;
609 };
610
Simon Glass5620cf82018-10-01 12:22:40 -0600[diff] [blame]611 pwm: pwm {
Simon Glasse62f4be2017-04-16 21:01:11 -0600[diff] [blame]612 compatible = "sandbox,pwm";
Simon Glass5620cf82018-10-01 12:22:40 -0600[diff] [blame]613 #pwm-cells = <2>;
Simon Glasse62f4be2017-04-16 21:01:11 -0600[diff] [blame]614 };
615
616 pwm2 {
617 compatible = "sandbox,pwm";
Simon Glass5620cf82018-10-01 12:22:40 -0600[diff] [blame]618 #pwm-cells = <2>;
Simon Glasse62f4be2017-04-16 21:01:11 -0600[diff] [blame]619 };
620
Simon Glass3d355e62015-07-06 12:54:31 -0600[diff] [blame]621 ram {
622 compatible = "sandbox,ram";
623 };
624
Simon Glassd860f222015-07-06 12:54:29 -0600[diff] [blame]625 reset@0 {
626 compatible = "sandbox,warm-reset";
627 };
628
629 reset@1 {
630 compatible = "sandbox,reset";
631 };
632
Stephen Warren6488e642016-06-17 09:43:59 -0600[diff] [blame]633 resetc: reset-ctl {
634 compatible = "sandbox,reset-ctl";
635 #reset-cells = <1>;
636 };
637
638 reset-ctl-test {
639 compatible = "sandbox,reset-ctl-test";
640 resets = <&resetc 100>, <&resetc 2>;
641 reset-names = "other", "test";
642 };
643
Sughosh Ganu23e37512019-12-28 23:58:31 +0530[diff] [blame]644 rng {
645 compatible = "sandbox,sandbox-rng";
646 };
647
Nishanth Menonedf85812015-09-17 15:42:41 -0500[diff] [blame]648 rproc_1: rproc@1 {
649 compatible = "sandbox,test-processor";
650 remoteproc-name = "remoteproc-test-dev1";
651 };
652
653 rproc_2: rproc@2 {
654 compatible = "sandbox,test-processor";
655 internal-memory-mapped;
656 remoteproc-name = "remoteproc-test-dev2";
657 };
658
Simon Glass5620cf82018-10-01 12:22:40 -0600[diff] [blame]659 panel {
660 compatible = "simple-panel";
661 backlight = <&backlight 0 100>;
662 };
663
Ramon Fried26ed32e2018-07-02 02:57:59 +0300[diff] [blame]664 smem@0 {
665 compatible = "sandbox,smem";
666 };
667
Simon Glass76072ac2018-12-10 10:37:36 -0700[diff] [blame]668 sound {
669 compatible = "sandbox,sound";
670 cpu {
671 sound-dai = <&i2s 0>;
672 };
673
674 codec {
675 sound-dai = <&audio 0>;
676 };
677 };
678
Simon Glass25348a42014-10-13 23:42:11 -0600[diff] [blame]679 spi@0 {
680 #address-cells = <1>;
681 #size-cells = <0>;
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]682 reg = <0 1>;
Simon Glass25348a42014-10-13 23:42:11 -0600[diff] [blame]683 compatible = "sandbox,spi";
684 cs-gpios = <0>, <&gpio_a 0>;
685 spi.bin@0 {
686 reg = <0>;
Neil Armstronga009fa72019-02-10 10:16:20 +0000[diff] [blame]687 compatible = "spansion,m25p16", "jedec,spi-nor";
Simon Glass25348a42014-10-13 23:42:11 -0600[diff] [blame]688 spi-max-frequency = <40000000>;
689 sandbox,filename = "spi.bin";
690 };
691 };
692
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +0100[diff] [blame]693 syscon0: syscon@0 {
Simon Glasscd556522015-07-06 12:54:35 -0600[diff] [blame]694 compatible = "sandbox,syscon0";
Mario Sixe3f59f42018-10-04 09:00:40 +0200[diff] [blame]695 reg = <0x10 16>;
Simon Glasscd556522015-07-06 12:54:35 -0600[diff] [blame]696 };
697
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +0100[diff] [blame]698 another_system_controller: syscon@1 {
Simon Glasscd556522015-07-06 12:54:35 -0600[diff] [blame]699 compatible = "sandbox,syscon1";
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]700 reg = <0x20 5
701 0x28 6
702 0x30 7
703 0x38 8>;
Simon Glasscd556522015-07-06 12:54:35 -0600[diff] [blame]704 };
705
Patrick Delaunayee010432019-03-07 09:57:13 +0100[diff] [blame]706 syscon2: syscon@2 {
Masahiro Yamada42ab1072018-04-23 13:26:53 +0900[diff] [blame]707 compatible = "simple-mfd", "syscon";
708 reg = <0x40 5
709 0x48 6
710 0x50 7
711 0x58 8>;
712 };
713
Thomas Chou6f2cfbf2015-12-11 16:27:34 +0800[diff] [blame]714 timer {
715 compatible = "sandbox,timer";
716 clock-frequency = <1000000>;
717 };
718
Miquel Raynal80938c12018-05-15 11:57:27 +0200[diff] [blame]719 tpm2 {
720 compatible = "sandbox,tpm2";
721 };
722
Simon Glass5b968632015-05-22 15:42:15 -0600[diff] [blame]723 uart0: serial {
724 compatible = "sandbox,serial";
725 u-boot,dm-pre-reloc;
Joe Hershberger4c197242015-03-22 17:09:15 -0500[diff] [blame]726 };
727
Simon Glass31680482015-03-25 12:23:05 -0600[diff] [blame]728 usb_0: usb@0 {
729 compatible = "sandbox,usb";
730 status = "disabled";
731 hub {
732 compatible = "sandbox,usb-hub";
733 #address-cells = <1>;
734 #size-cells = <0>;
735 flash-stick {
736 reg = <0>;
737 compatible = "sandbox,usb-flash";
738 };
739 };
740 };
741
742 usb_1: usb@1 {
743 compatible = "sandbox,usb";
744 hub {
745 compatible = "usb-hub";
746 usb,device-class = <9>;
747 hub-emul {
748 compatible = "sandbox,usb-hub";
749 #address-cells = <1>;
750 #size-cells = <0>;
Simon Glass4700fe52015-11-08 23:48:01 -0700[diff] [blame]751 flash-stick@0 {
Simon Glass31680482015-03-25 12:23:05 -0600[diff] [blame]752 reg = <0>;
753 compatible = "sandbox,usb-flash";
754 sandbox,filepath = "testflash.bin";
755 };
756
Simon Glass4700fe52015-11-08 23:48:01 -0700[diff] [blame]757 flash-stick@1 {
758 reg = <1>;
759 compatible = "sandbox,usb-flash";
760 sandbox,filepath = "testflash1.bin";
761 };
762
763 flash-stick@2 {
764 reg = <2>;
765 compatible = "sandbox,usb-flash";
766 sandbox,filepath = "testflash2.bin";
767 };
768
Simon Glassc0ccc722015-11-08 23:48:08 -0700[diff] [blame]769 keyb@3 {
770 reg = <3>;
771 compatible = "sandbox,usb-keyb";
772 };
773
Simon Glass31680482015-03-25 12:23:05 -0600[diff] [blame]774 };
775 };
776 };
777
778 usb_2: usb@2 {
779 compatible = "sandbox,usb";
780 status = "disabled";
781 };
782
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +0200[diff] [blame]783 spmi: spmi@0 {
784 compatible = "sandbox,spmi";
785 #address-cells = <0x1>;
786 #size-cells = <0x1>;
Simon Glass95139972019-09-25 08:55:59 -0600[diff] [blame]787 ranges;
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +0200[diff] [blame]788 pm8916@0 {
789 compatible = "qcom,spmi-pmic";
790 reg = <0x0 0x1>;
791 #address-cells = <0x1>;
792 #size-cells = <0x1>;
Simon Glass95139972019-09-25 08:55:59 -0600[diff] [blame]793 ranges;
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +0200[diff] [blame]794
795 spmi_gpios: gpios@c000 {
796 compatible = "qcom,pm8916-gpio";
797 reg = <0xc000 0x400>;
798 gpio-controller;
799 gpio-count = <4>;
800 #gpio-cells = <2>;
801 gpio-bank-name="spmi";
802 };
803 };
804 };
maxims@google.comdaea6d42017-04-17 12:00:21 -0700[diff] [blame]805
806 wdt0: wdt@0 {
807 compatible = "sandbox,wdt";
808 };
Rob Clarka471b672018-01-10 11:33:30 +0100[diff] [blame]809
Mario Six95922152018-08-09 14:51:19 +0200[diff] [blame]810 axi: axi@0 {
811 compatible = "sandbox,axi";
812 #address-cells = <0x1>;
813 #size-cells = <0x1>;
814 store@0 {
815 compatible = "sandbox,sandbox_store";
816 reg = <0x0 0x400>;
817 };
818 };
819
Rob Clarka471b672018-01-10 11:33:30 +0100[diff] [blame]820 chosen {
Simon Glass305ac9a2018-02-03 10:36:58 -0700[diff] [blame]821 #address-cells = <1>;
822 #size-cells = <1>;
Simon Glassf3455962020-01-27 08:49:43 -0700[diff] [blame]823 setting = "sunrise ohoka";
824 other-node = "/some-bus/c-test@5";
Simon Glasse09223c2020-01-27 08:49:46 -0700[diff] [blame]825 int-values = <0x1937 72993>;
Rob Clarka471b672018-01-10 11:33:30 +0100[diff] [blame]826 chosen-test {
827 compatible = "denx,u-boot-fdt-test";
828 reg = <9 1>;
829 };
830 };
Mario Six35616ef2018-03-12 14:53:33 +0100[diff] [blame]831
832 translation-test@8000 {
833 compatible = "simple-bus";
834 reg = <0x8000 0x4000>;
835
836 #address-cells = <0x2>;
837 #size-cells = <0x1>;
838
839 ranges = <0 0x0 0x8000 0x1000
840 1 0x100 0x9000 0x1000
841 2 0x200 0xA000 0x1000
842 3 0x300 0xB000 0x1000
843 >;
844
Fabien Dessenne22236e02019-05-31 15:11:30 +0200[diff] [blame]845 dma-ranges = <0 0x000 0x10000000 0x1000
846 1 0x100 0x20000000 0x1000
847 >;
848
Mario Six35616ef2018-03-12 14:53:33 +0100[diff] [blame]849 dev@0,0 {
850 compatible = "denx,u-boot-fdt-dummy";
851 reg = <0 0x0 0x1000>;
Álvaro Fernández Rojasa3181152018-12-03 19:37:09 +0100[diff] [blame]852 reg-names = "sandbox-dummy-0";
Mario Six35616ef2018-03-12 14:53:33 +0100[diff] [blame]853 };
854
855 dev@1,100 {
856 compatible = "denx,u-boot-fdt-dummy";
857 reg = <1 0x100 0x1000>;
858
859 };
860
861 dev@2,200 {
862 compatible = "denx,u-boot-fdt-dummy";
863 reg = <2 0x200 0x1000>;
864 };
865
866
867 noxlatebus@3,300 {
868 compatible = "simple-bus";
869 reg = <3 0x300 0x1000>;
870
871 #address-cells = <0x1>;
872 #size-cells = <0x0>;
873
874 dev@42 {
875 compatible = "denx,u-boot-fdt-dummy";
876 reg = <0x42>;
877 };
878 };
879 };
Mario Six02ad6fb2018-09-27 09:19:31 +0200[diff] [blame]880
881 osd {
882 compatible = "sandbox,sandbox_osd";
883 };
Tom Rinib93eea72018-09-30 18:16:51 -0400[diff] [blame]884
Mario Sixab664ff2018-07-31 11:44:13 +0200[diff] [blame]885 board {
886 compatible = "sandbox,board_sandbox";
887 };
Jens Wiklander86afaa62018-09-25 16:40:16 +0200[diff] [blame]888
889 sandbox_tee {
890 compatible = "sandbox,tee";
891 };
Bin Meng1bb290d2018-10-15 02:21:26 -0700[diff] [blame]892
893 sandbox_virtio1 {
894 compatible = "sandbox,virtio1";
895 };
896
897 sandbox_virtio2 {
898 compatible = "sandbox,virtio2";
899 };
Patrice Chotard0fc8afc2018-10-24 14:10:23 +0200[diff] [blame]900
901 pinctrl {
902 compatible = "sandbox,pinctrl";
903 };
Benjamin Gaignarda550b542018-11-27 13:49:50 +0100[diff] [blame]904
905 hwspinlock@0 {
906 compatible = "sandbox,hwspinlock";
907 };
Grygorii Strashko19ebf0b2018-11-28 19:17:51 +0100[diff] [blame]908
909 dma: dma {
910 compatible = "sandbox,dma";
911 #dma-cells = <1>;
912
913 dmas = <&dma 0>, <&dma 1>, <&dma 2>;
914 dma-names = "m2m", "tx0", "rx0";
915 };
Alex Marginean0daa53a2019-06-03 19:12:28 +0300[diff] [blame]916
Alex Marginean0649be52019-07-12 10:13:53 +0300[diff] [blame]917 /*
918 * keep mdio-mux ahead of mdio so that the mux is removed first at the
919 * end of the test. If parent mdio is removed first, clean-up of the
920 * mux will trigger a 2nd probe of parent-mdio, leaving parent-mdio
921 * active at the end of the test. That it turn doesn't allow the mdio
922 * class to be destroyed, triggering an error.
923 */
924 mdio-mux-test {
925 compatible = "sandbox,mdio-mux";
926 #address-cells = <1>;
927 #size-cells = <0>;
928 mdio-parent-bus = <&mdio>;
929
930 mdio-ch-test@0 {
931 reg = <0>;
932 };
933 mdio-ch-test@1 {
934 reg = <1>;
935 };
936 };
937
938 mdio: mdio-test {
Alex Marginean0daa53a2019-06-03 19:12:28 +0300[diff] [blame]939 compatible = "sandbox,mdio";
940 };
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]941};
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200[diff] [blame]942
943#include "sandbox_pmic.dtsi"