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Dirk Behmee0e49fe2008-12-14 09:47:15 +01001/*
2 *
3 * Common board functions for OMAP3 based boards.
4 *
5 * (C) Copyright 2004-2008
6 * Texas Instruments, <www.ti.com>
7 *
8 * Author :
9 * Sunil Kumar <sunilsaini05@gmail.com>
10 * Shashi Ranjan <shashiranjanmca05@gmail.com>
11 *
12 * Derived from Beagle Board and 3430 SDP code by
13 * Richard Woodruff <r-woodruff2@ti.com>
14 * Syed Mohammed Khasim <khasim@ti.com>
15 *
16 *
17 * See file CREDITS for list of people who contributed to this
18 * project.
19 *
20 * This program is free software; you can redistribute it and/or
21 * modify it under the terms of the GNU General Public License as
22 * published by the Free Software Foundation; either version 2 of
23 * the License, or (at your option) any later version.
24 *
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
29 *
30 * You should have received a copy of the GNU General Public License
31 * along with this program; if not, write to the Free Software
32 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
33 * MA 02111-1307 USA
34 */
35#include <common.h>
36#include <asm/io.h>
37#include <asm/arch/sys_proto.h>
38#include <asm/arch/mem.h>
Kim, Heung Jun3b5ac952009-06-20 11:02:17 +020039#include <asm/cache.h>
Aneesh Vd16dd012011-06-16 23:30:53 +000040#include <asm/armv7.h>
Aneesh V1843eca2011-07-31 20:30:53 +000041#include <asm/arch/gpio.h>
Simon Schwarz992dcf72011-09-14 15:29:26 -040042#include <asm/omap_common.h>
Dirk Behmee0e49fe2008-12-14 09:47:15 +010043
Aneesh Vd16dd012011-06-16 23:30:53 +000044/* Declarations */
Dirk Behmee0e49fe2008-12-14 09:47:15 +010045extern omap3_sysinfo sysinfo;
Aneesh Vd16dd012011-06-16 23:30:53 +000046static void omap3_setup_aux_cr(void);
47static void omap3_invalidate_l2_cache_secure(void);
Dirk Behmee0e49fe2008-12-14 09:47:15 +010048
Aneesh V9a390882011-07-21 09:29:29 -040049static const struct gpio_bank gpio_bank_34xx[6] = {
50 { (void *)OMAP34XX_GPIO1_BASE, METHOD_GPIO_24XX },
51 { (void *)OMAP34XX_GPIO2_BASE, METHOD_GPIO_24XX },
52 { (void *)OMAP34XX_GPIO3_BASE, METHOD_GPIO_24XX },
53 { (void *)OMAP34XX_GPIO4_BASE, METHOD_GPIO_24XX },
54 { (void *)OMAP34XX_GPIO5_BASE, METHOD_GPIO_24XX },
55 { (void *)OMAP34XX_GPIO6_BASE, METHOD_GPIO_24XX },
56};
57
58const struct gpio_bank *const omap_gpio_bank = gpio_bank_34xx;
59
Simon Schwarz992dcf72011-09-14 15:29:26 -040060#ifdef CONFIG_SPL_BUILD
61/*
62* We use static variables because global data is not ready yet.
63* Initialized data is available in SPL right from the beginning.
64* We would not typically need to save these parameters in regular
65* U-Boot. This is needed only in SPL at the moment.
66*/
67u32 omap3_boot_device = BOOT_DEVICE_NAND;
68
69/* auto boot mode detection is not possible for OMAP3 - hard code */
70u32 omap_boot_mode(void)
71{
72 switch (omap_boot_device()) {
73 case BOOT_DEVICE_MMC2:
74 return MMCSD_MODE_RAW;
75 case BOOT_DEVICE_MMC1:
76 return MMCSD_MODE_FAT;
77 break;
78 case BOOT_DEVICE_NAND:
79 return NAND_MODE_HW_ECC;
80 break;
81 default:
82 puts("spl: ERROR: unknown device - can't select boot mode\n");
83 hang();
84 }
85}
86
87u32 omap_boot_device(void)
88{
89 return omap3_boot_device;
90}
91
92#endif /* CONFIG_SPL_BUILD */
93
94
Dirk Behmee0e49fe2008-12-14 09:47:15 +010095/******************************************************************************
96 * Routine: delay
97 * Description: spinning delay to use before udelay works
98 *****************************************************************************/
99static inline void delay(unsigned long loops)
100{
101 __asm__ volatile ("1:\n" "subs %0, %1, #1\n"
102 "bne 1b":"=r" (loops):"0"(loops));
103}
104
105/******************************************************************************
106 * Routine: secure_unlock
107 * Description: Setup security registers for access
108 * (GP Device only)
109 *****************************************************************************/
110void secure_unlock_mem(void)
111{
Dirk Behmedc7af202009-08-08 09:30:21 +0200112 struct pm *pm_rt_ape_base = (struct pm *)PM_RT_APE_BASE_ADDR_ARM;
113 struct pm *pm_gpmc_base = (struct pm *)PM_GPMC_BASE_ADDR_ARM;
114 struct pm *pm_ocm_ram_base = (struct pm *)PM_OCM_RAM_BASE_ADDR_ARM;
115 struct pm *pm_iva2_base = (struct pm *)PM_IVA2_BASE_ADDR_ARM;
116 struct sms *sms_base = (struct sms *)OMAP34XX_SMS_BASE;
Dirk Behmee0e49fe2008-12-14 09:47:15 +0100117
118 /* Protection Module Register Target APE (PM_RT) */
119 writel(UNLOCK_1, &pm_rt_ape_base->req_info_permission_1);
120 writel(UNLOCK_1, &pm_rt_ape_base->read_permission_0);
121 writel(UNLOCK_1, &pm_rt_ape_base->wirte_permission_0);
122 writel(UNLOCK_2, &pm_rt_ape_base->addr_match_1);
123
124 writel(UNLOCK_3, &pm_gpmc_base->req_info_permission_0);
125 writel(UNLOCK_3, &pm_gpmc_base->read_permission_0);
126 writel(UNLOCK_3, &pm_gpmc_base->wirte_permission_0);
127
128 writel(UNLOCK_3, &pm_ocm_ram_base->req_info_permission_0);
129 writel(UNLOCK_3, &pm_ocm_ram_base->read_permission_0);
130 writel(UNLOCK_3, &pm_ocm_ram_base->wirte_permission_0);
131 writel(UNLOCK_2, &pm_ocm_ram_base->addr_match_2);
132
133 /* IVA Changes */
134 writel(UNLOCK_3, &pm_iva2_base->req_info_permission_0);
135 writel(UNLOCK_3, &pm_iva2_base->read_permission_0);
136 writel(UNLOCK_3, &pm_iva2_base->wirte_permission_0);
137
138 /* SDRC region 0 public */
139 writel(UNLOCK_1, &sms_base->rg_att0);
140}
141
142/******************************************************************************
143 * Routine: secureworld_exit()
144 * Description: If chip is EMU and boot type is external
145 * configure secure registers and exit secure world
146 * general use.
147 *****************************************************************************/
148void secureworld_exit()
149{
150 unsigned long i;
151
152 /* configrue non-secure access control register */
153 __asm__ __volatile__("mrc p15, 0, %0, c1, c1, 2":"=r"(i));
154 /* enabling co-processor CP10 and CP11 accesses in NS world */
155 __asm__ __volatile__("orr %0, %0, #0xC00":"=r"(i));
156 /*
157 * allow allocation of locked TLBs and L2 lines in NS world
158 * allow use of PLE registers in NS world also
159 */
160 __asm__ __volatile__("orr %0, %0, #0x70000":"=r"(i));
161 __asm__ __volatile__("mcr p15, 0, %0, c1, c1, 2":"=r"(i));
162
163 /* Enable ASA in ACR register */
164 __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
165 __asm__ __volatile__("orr %0, %0, #0x10":"=r"(i));
166 __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i));
167
168 /* Exiting secure world */
169 __asm__ __volatile__("mrc p15, 0, %0, c1, c1, 0":"=r"(i));
170 __asm__ __volatile__("orr %0, %0, #0x31":"=r"(i));
171 __asm__ __volatile__("mcr p15, 0, %0, c1, c1, 0":"=r"(i));
172}
173
174/******************************************************************************
Dirk Behmee0e49fe2008-12-14 09:47:15 +0100175 * Routine: try_unlock_sram()
176 * Description: If chip is GP/EMU(special) type, unlock the SRAM for
177 * general use.
178 *****************************************************************************/
179void try_unlock_memory()
180{
181 int mode;
182 int in_sdram = is_running_in_sdram();
183
184 /*
185 * if GP device unlock device SRAM for general use
186 * secure code breaks for Secure/Emulation device - HS/E/T
187 */
188 mode = get_device_type();
189 if (mode == GP_DEVICE)
190 secure_unlock_mem();
191
192 /*
193 * If device is EMU and boot is XIP external booting
194 * Unlock firewalls and disable L2 and put chip
195 * out of secure world
196 *
197 * Assuming memories are unlocked by the demon who put us in SDRAM
198 */
199 if ((mode <= EMU_DEVICE) && (get_boot_type() == 0x1F)
200 && (!in_sdram)) {
201 secure_unlock_mem();
202 secureworld_exit();
203 }
204
205 return;
206}
207
208/******************************************************************************
209 * Routine: s_init
210 * Description: Does early system init of muxing and clocks.
211 * - Called path is with SRAM stack.
212 *****************************************************************************/
213void s_init(void)
214{
215 int in_sdram = is_running_in_sdram();
216
217 watchdog_init();
218
219 try_unlock_memory();
220
Aneesh Vd16dd012011-06-16 23:30:53 +0000221 /* Errata workarounds */
222 omap3_setup_aux_cr();
Dirk Behmee0e49fe2008-12-14 09:47:15 +0100223
Aneesh Vd16dd012011-06-16 23:30:53 +0000224#ifndef CONFIG_SYS_L2CACHE_OFF
225 /* Invalidate L2-cache from secure mode */
226 omap3_invalidate_l2_cache_secure();
Dirk Behmee0e49fe2008-12-14 09:47:15 +0100227#endif
Dirk Behmee0e49fe2008-12-14 09:47:15 +0100228
229 set_muxconf_regs();
230 delay(100);
231
232 prcm_init();
233
234 per_clocks_enable();
235
Simon Schwarz992dcf72011-09-14 15:29:26 -0400236#ifdef CONFIG_SPL_BUILD
237 preloader_console_init();
238#endif
239
Dirk Behmee0e49fe2008-12-14 09:47:15 +0100240 if (!in_sdram)
Vaibhav Hiremath558d23d2010-06-07 15:20:34 -0400241 mem_init();
Dirk Behmee0e49fe2008-12-14 09:47:15 +0100242}
243
244/******************************************************************************
245 * Routine: wait_for_command_complete
246 * Description: Wait for posting to finish on watchdog
247 *****************************************************************************/
Dirk Behmedc7af202009-08-08 09:30:21 +0200248void wait_for_command_complete(struct watchdog *wd_base)
Dirk Behmee0e49fe2008-12-14 09:47:15 +0100249{
250 int pending = 1;
251 do {
252 pending = readl(&wd_base->wwps);
253 } while (pending);
254}
255
256/******************************************************************************
257 * Routine: watchdog_init
258 * Description: Shut down watch dogs
259 *****************************************************************************/
260void watchdog_init(void)
261{
Dirk Behmedc7af202009-08-08 09:30:21 +0200262 struct watchdog *wd2_base = (struct watchdog *)WD2_BASE;
263 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
Dirk Behmee0e49fe2008-12-14 09:47:15 +0100264
265 /*
266 * There are 3 watch dogs WD1=Secure, WD2=MPU, WD3=IVA. WD1 is
267 * either taken care of by ROM (HS/EMU) or not accessible (GP).
268 * We need to take care of WD2-MPU or take a PRCM reset. WD3
269 * should not be running and does not generate a PRCM reset.
270 */
271
272 sr32(&prcm_base->fclken_wkup, 5, 1, 1);
273 sr32(&prcm_base->iclken_wkup, 5, 1, 1);
274 wait_on_value(ST_WDT2, 0x20, &prcm_base->idlest_wkup, 5);
275
276 writel(WD_UNLOCK1, &wd2_base->wspr);
277 wait_for_command_complete(wd2_base);
278 writel(WD_UNLOCK2, &wd2_base->wspr);
279}
280
281/******************************************************************************
Dirk Behmee0e49fe2008-12-14 09:47:15 +0100282 * Dummy function to handle errors for EABI incompatibility
283 *****************************************************************************/
Dirk Behmee0e49fe2008-12-14 09:47:15 +0100284void abort(void)
285{
286}
287
Simon Schwarz992dcf72011-09-14 15:29:26 -0400288#if defined(CONFIG_NAND_OMAP_GPMC) & !defined(CONFIG_SPL_BUILD)
Dirk Behmee0e49fe2008-12-14 09:47:15 +0100289/******************************************************************************
290 * OMAP3 specific command to switch between NAND HW and SW ecc
291 *****************************************************************************/
Wolfgang Denk6262d0212010-06-28 22:00:46 +0200292static int do_switch_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
Dirk Behmee0e49fe2008-12-14 09:47:15 +0100293{
294 if (argc != 2)
295 goto usage;
296 if (strncmp(argv[1], "hw", 2) == 0)
297 omap_nand_switch_ecc(1);
298 else if (strncmp(argv[1], "sw", 2) == 0)
299 omap_nand_switch_ecc(0);
300 else
301 goto usage;
302
303 return 0;
304
305usage:
Sanjeev Premi15af9982009-04-03 14:00:07 +0530306 printf ("Usage: nandecc %s\n", cmdtp->usage);
Dirk Behmee0e49fe2008-12-14 09:47:15 +0100307 return 1;
308}
309
310U_BOOT_CMD(
311 nandecc, 2, 1, do_switch_ecc,
Robert P. J. Day3ea16c32009-11-17 07:30:23 -0500312 "switch OMAP3 NAND ECC calculation algorithm",
Wolfgang Denkc54781c2009-05-24 17:06:54 +0200313 "[hw/sw] - Switch between NAND hardware (hw) or software (sw) ecc algorithm"
314);
Dirk Behmee0e49fe2008-12-14 09:47:15 +0100315
Simon Schwarz992dcf72011-09-14 15:29:26 -0400316#endif /* CONFIG_NAND_OMAP_GPMC & !CONFIG_SPL_BUILD */
Sanjeev Premie32ef2e2009-04-27 21:27:27 +0530317
318#ifdef CONFIG_DISPLAY_BOARDINFO
319/**
320 * Print board information
321 */
322int checkboard (void)
323{
324 char *mem_s ;
325
326 if (is_mem_sdr())
327 mem_s = "mSDR";
328 else
329 mem_s = "LPDDR";
330
331 printf("%s + %s/%s\n", sysinfo.board_string, mem_s,
332 sysinfo.nand_string);
333
334 return 0;
335}
336#endif /* CONFIG_DISPLAY_BOARDINFO */
Aneesh Vd16dd012011-06-16 23:30:53 +0000337
338static void omap3_emu_romcode_call(u32 service_id, u32 *parameters)
339{
340 u32 i, num_params = *parameters;
341 u32 *sram_scratch_space = (u32 *)OMAP3_PUBLIC_SRAM_SCRATCH_AREA;
342
343 /*
344 * copy the parameters to an un-cached area to avoid coherency
345 * issues
346 */
347 for (i = 0; i < num_params; i++) {
348 __raw_writel(*parameters, sram_scratch_space);
349 parameters++;
350 sram_scratch_space++;
351 }
352
353 /* Now make the PPA call */
354 do_omap3_emu_romcode_call(service_id, OMAP3_PUBLIC_SRAM_SCRATCH_AREA);
355}
356
357static void omap3_update_aux_cr_secure(u32 set_bits, u32 clear_bits)
358{
359 u32 acr;
360
361 /* Read ACR */
362 asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
363 acr &= ~clear_bits;
364 acr |= set_bits;
365
366 if (get_device_type() == GP_DEVICE) {
367 omap3_gp_romcode_call(OMAP3_GP_ROMCODE_API_WRITE_ACR,
368 acr);
369 } else {
370 struct emu_hal_params emu_romcode_params;
371 emu_romcode_params.num_params = 1;
372 emu_romcode_params.param1 = acr;
373 omap3_emu_romcode_call(OMAP3_EMU_HAL_API_WRITE_ACR,
374 (u32 *)&emu_romcode_params);
375 }
376}
377
378static void omap3_update_aux_cr(u32 set_bits, u32 clear_bits)
379{
380 u32 acr;
381
382 /* Read ACR */
383 asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
384 acr &= ~clear_bits;
385 acr |= set_bits;
386
387 /* Write ACR - affects non-secure banked bits */
388 asm volatile ("mcr p15, 0, %0, c1, c0, 1" : : "r" (acr));
389}
390
391static void omap3_setup_aux_cr(void)
392{
393 /* Workaround for Cortex-A8 errata: #454179 #430973
394 * Set "IBE" bit
395 * Set "Disable Brach Size Mispredicts" bit
396 * Workaround for erratum #621766
397 * Enable L1NEON bit
398 * ACR |= (IBE | DBSM | L1NEON) => ACR |= 0xE0
399 */
400 omap3_update_aux_cr_secure(0xE0, 0);
401}
402
403#ifndef CONFIG_SYS_L2CACHE_OFF
404/* Invalidate the entire L2 cache from secure mode */
405static void omap3_invalidate_l2_cache_secure(void)
406{
407 if (get_device_type() == GP_DEVICE) {
408 omap3_gp_romcode_call(OMAP3_GP_ROMCODE_API_L2_INVAL,
409 0);
410 } else {
411 struct emu_hal_params emu_romcode_params;
412 emu_romcode_params.num_params = 1;
413 emu_romcode_params.param1 = 0;
414 omap3_emu_romcode_call(OMAP3_EMU_HAL_API_L2_INVAL,
415 (u32 *)&emu_romcode_params);
416 }
417}
418
419void v7_outer_cache_enable(void)
420{
421 /* Set L2EN */
422 omap3_update_aux_cr_secure(0x2, 0);
423
424 /*
425 * On some revisions L2EN bit is banked on some revisions it's not
426 * No harm in setting both banked bits(in fact this is required
427 * by an erratum)
428 */
429 omap3_update_aux_cr(0x2, 0);
430}
431
432void v7_outer_cache_disable(void)
433{
434 /* Clear L2EN */
435 omap3_update_aux_cr_secure(0, 0x2);
436
437 /*
438 * On some revisions L2EN bit is banked on some revisions it's not
439 * No harm in clearing both banked bits(in fact this is required
440 * by an erratum)
441 */
442 omap3_update_aux_cr(0, 0x2);
443}
444#endif
Aneesh V572134b2011-08-11 04:35:43 +0000445
446#ifndef CONFIG_SYS_DCACHE_OFF
447void enable_caches(void)
448{
449 /* Enable D-cache. I-cache is already enabled in start.S */
450 dcache_enable();
451}
452#endif