Chandan Nath | 7d74410 | 2011-10-14 02:58:26 +0000 | [diff] [blame] | 1 | /* |
| 2 | * board.c |
| 3 | * |
| 4 | * Common board functions for AM33XX based boards |
| 5 | * |
| 6 | * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or |
| 9 | * modify it under the terms of the GNU General Public License as |
| 10 | * published by the Free Software Foundation; either version 2 of |
| 11 | * the License, or (at your option) any later version. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | */ |
| 18 | |
| 19 | #include <common.h> |
| 20 | #include <asm/arch/cpu.h> |
| 21 | #include <asm/arch/hardware.h> |
| 22 | #include <asm/arch/ddr_defs.h> |
| 23 | #include <asm/arch/clock.h> |
| 24 | #include <asm/io.h> |
| 25 | |
| 26 | DECLARE_GLOBAL_DATA_PTR; |
| 27 | |
| 28 | struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE; |
| 29 | struct timer_reg *timerreg = (struct timer_reg *)DM_TIMER2_BASE; |
| 30 | |
| 31 | /* |
| 32 | * early system init of muxing and clocks. |
| 33 | */ |
| 34 | void s_init(u32 in_ddr) |
| 35 | { |
| 36 | /* WDT1 is already running when the bootloader gets control |
| 37 | * Disable it to avoid "random" resets |
| 38 | */ |
| 39 | writel(0xAAAA, &wdtimer->wdtwspr); |
| 40 | while (readl(&wdtimer->wdtwwps) != 0x0) |
| 41 | ; |
| 42 | writel(0x5555, &wdtimer->wdtwspr); |
| 43 | while (readl(&wdtimer->wdtwwps) != 0x0) |
| 44 | ; |
| 45 | |
| 46 | /* Setup the PLLs and the clocks for the peripherals */ |
| 47 | #ifdef CONFIG_SETUP_PLL |
| 48 | pll_init(); |
| 49 | #endif |
| 50 | if (!in_ddr) |
| 51 | config_ddr(); |
| 52 | } |
| 53 | |
| 54 | /* Initialize timer */ |
| 55 | void init_timer(void) |
| 56 | { |
| 57 | /* Reset the Timer */ |
| 58 | writel(0x2, (&timerreg->tsicrreg)); |
| 59 | |
| 60 | /* Wait until the reset is done */ |
| 61 | while (readl(&timerreg->tiocpcfgreg) & 1) |
| 62 | ; |
| 63 | |
| 64 | /* Start the Timer */ |
| 65 | writel(0x1, (&timerreg->tclrreg)); |
| 66 | } |