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git01.mediatek.com / filogic / uboot / c6eb9e76bd459c777b41bc9b699fd9ac9366cd3b / . / arch / arm / dts / fsl-ls1028a-qds.dts
blob: 3fd37beedf4f834e479d6deb73f992ee8f11b90c [file] [log] [blame]
Yuantian Tang473bbc42019-04-10 16:43:35 +0800[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+ OR X11
2/*
3 * NXP ls1028AQDS device tree source
4 *
5 * Copyright 2019 NXP
6 *
7 */
8
9/dts-v1/;
10
11#include "fsl-ls1028a.dtsi"
12
13/ {
14 model = "NXP Layerscape 1028a QDS Board";
15 compatible = "fsl,ls1028a-qds", "fsl,ls1028a";
Kuldeep Singhbaab2462019-11-06 16:38:00 +0530[diff] [blame]16 aliases {
17 spi0 = &fspi;
18 };
19
Yuantian Tang473bbc42019-04-10 16:43:35 +0800[diff] [blame]20};
21
22&dspi0 {
23 status = "okay";
24};
25
26&dspi1 {
27 status = "okay";
28};
29
30&dspi2 {
31 status = "okay";
32};
33
34&esdhc0 {
35 status = "okay";
36};
37
38&esdhc1 {
39 status = "okay";
Alex Marginean679cd542019-08-07 19:30:03 +0300[diff] [blame]40
Kuldeep Singhbaab2462019-11-06 16:38:00 +0530[diff] [blame]41};
42
43&fspi {
44 status = "okay";
45
46 mt35xu02g0: flash@0 {
47 #address-cells = <1>;
48 #size-cells = <1>;
49 compatible = "jedec,spi-nor";
50 spi-max-frequency = <50000000>;
51 reg = <0>;
52 };
Yuantian Tang473bbc42019-04-10 16:43:35 +0800[diff] [blame]53};
54
55&i2c0 {
56 status = "okay";
Chuanhua Hanc6c006a2019-07-10 15:48:39 +0800[diff] [blame]57 u-boot,dm-pre-reloc;
58
Alex Marginean679cd542019-08-07 19:30:03 +0300[diff] [blame]59 fpga@66 {
60 #address-cells = <1>;
61 #size-cells = <0>;
62 compatible = "simple-mfd";
63 reg = <0x66>;
64
65 mux-mdio@54 {
66 #address-cells = <1>;
67 #size-cells = <0>;
68 compatible = "mdio-mux-i2creg";
69 reg = <0x54>;
70 #mux-control-cells = <1>;
71 mux-reg-masks = <0x54 0xf0>;
72 mdio-parent-bus = <&mdio0>;
73
74 /* on-board MDIO with a single RGMII PHY */
75 mdio@00 {
76 #address-cells = <1>;
77 #size-cells = <0>;
78 reg = <0x00>;
79
80 qds_phy0: phy@5 {
81 reg = <5>;
82 };
83 };
84 /* slot 1 */
85 slot1: mdio@40 {
86 #address-cells = <1>;
87 #size-cells = <0>;
88 reg = <0x40>;
89 };
90 /* slot 2 */
91 slot2: mdio@50 {
92 #address-cells = <1>;
93 #size-cells = <0>;
94 reg = <0x50>;
95 };
96 /* slot 3 */
97 slot3: mdio@60 {
98 #address-cells = <1>;
99 #size-cells = <0>;
100 reg = <0x60>;
101 };
102 /* slot 4 */
103 slot4: mdio@70 {
104 #address-cells = <1>;
105 #size-cells = <0>;
106 reg = <0x70>;
107 };
108 };
109 };
110
Chuanhua Hanc6c006a2019-07-10 15:48:39 +0800[diff] [blame]111 i2c-mux@77 {
112 compatible = "nxp,pca9547";
113 reg = <0x77>;
114 #address-cells = <1>;
115 #size-cells = <0>;
116 };
Yuantian Tang473bbc42019-04-10 16:43:35 +0800[diff] [blame]117};
118
119&i2c1 {
120 status = "okay";
Chuanhua Han7657bc32019-07-10 15:48:40 +0800[diff] [blame]121
122 rtc@51 {
123 compatible = "pcf2127-rtc";
124 reg = <0x51>;
125 };
Yuantian Tang473bbc42019-04-10 16:43:35 +0800[diff] [blame]126};
127
128&i2c2 {
129 status = "okay";
130};
131
132&i2c3 {
133 status = "okay";
134};
135
136&i2c4 {
137 status = "okay";
138};
139
140&i2c5 {
141 status = "okay";
142};
143
144&i2c6 {
145 status = "okay";
146};
147
148&i2c7 {
149 status = "okay";
150};
151
152&sata {
153 status = "okay";
154};
155
156&serial0 {
157 status = "okay";
158};
159
160&serial1 {
161 status = "okay";
162};
163
164&usb1 {
165 status = "okay";
166};
167
168&usb2 {
169 status = "okay";
170};
Alex Marginean3be715e2019-07-03 12:11:43 +0300[diff] [blame]171
172&enetc1 {
173 status = "okay";
174 phy-mode = "rgmii";
175 phy-handle = <&qds_phy0>;
176};
177
178&mdio0 {
179 status = "okay";
Alex Marginean3be715e2019-07-03 12:11:43 +0300[diff] [blame]180};