wdenk | 97e8bda | 2004-09-29 22:43:59 +0000 | [diff] [blame] | 1 | /* $Id: xipif_v1_23_b.h,v 1.1 2002/03/18 23:24:52 linnj Exp $ */ |
wdenk | e537b3b | 2004-02-23 23:54:43 +0000 | [diff] [blame] | 2 | /****************************************************************************** |
| 3 | * |
wdenk | 97e8bda | 2004-09-29 22:43:59 +0000 | [diff] [blame] | 4 | * XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" |
| 5 | * AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND |
| 6 | * SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, |
| 7 | * OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, |
| 8 | * APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION |
| 9 | * THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, |
| 10 | * AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE |
| 11 | * FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY |
| 12 | * WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE |
| 13 | * IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR |
| 14 | * REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF |
| 15 | * INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS |
| 16 | * FOR A PARTICULAR PURPOSE. |
wdenk | e537b3b | 2004-02-23 23:54:43 +0000 | [diff] [blame] | 17 | * |
wdenk | 97e8bda | 2004-09-29 22:43:59 +0000 | [diff] [blame] | 18 | * (c) Copyright 2002 Xilinx Inc. |
| 19 | * All rights reserved. |
wdenk | e537b3b | 2004-02-23 23:54:43 +0000 | [diff] [blame] | 20 | * |
| 21 | ******************************************************************************/ |
| 22 | /****************************************************************************** |
| 23 | * |
| 24 | * FILENAME: |
| 25 | * |
| 26 | * xipif.h |
| 27 | * |
| 28 | * DESCRIPTION: |
| 29 | * |
| 30 | * The XIpIf component encapsulates the IPIF, which is the standard interface |
| 31 | * that IP must adhere to when connecting to a bus. The purpose of this |
| 32 | * component is to encapsulate the IPIF processing such that maintainability |
| 33 | * is increased. This component does not provide a lot of abstraction from |
| 34 | * from the details of the IPIF as it is considered a building block for |
| 35 | * device drivers. A device driver designer must be familiar with the |
| 36 | * details of the IPIF hardware to use this component. |
| 37 | * |
| 38 | * The IPIF hardware provides a building block for all hardware devices such |
| 39 | * that each device does not need to reimplement these building blocks. The |
| 40 | * IPIF contains other building blocks, such as FIFOs and DMA channels, which |
| 41 | * are also common to many devices. These blocks are implemented as separate |
| 42 | * hardware blocks and instantiated within the IPIF. The primary hardware of |
| 43 | * the IPIF which is implemented by this software component is the interrupt |
| 44 | * architecture. Since there are many blocks of a device which may generate |
| 45 | * interrupts, all the interrupt processing is contained in the common part |
| 46 | * of the device, the IPIF. This interrupt processing is for the device level |
| 47 | * only and does not include any processing for the interrupt controller. |
| 48 | * |
| 49 | * A device is a mechanism such as an Ethernet MAC. The device is made |
| 50 | * up of several parts which include an IPIF and the IP. The IPIF contains most |
| 51 | * of the device infrastructure which is common to all devices, such as |
| 52 | * interrupt processing, DMA channels, and FIFOs. The infrastructure may also |
| 53 | * be referred to as IPIF internal blocks since they are part of the IPIF and |
| 54 | * are separate blocks that can be selected based upon the needs of the device. |
| 55 | * The IP of the device is the logic that is unique to the device and interfaces |
| 56 | * to the IPIF of the device. |
| 57 | * |
| 58 | * In general, there are two levels of registers within the IPIF. The first |
| 59 | * level, referred to as the device level, contains registers which are for the |
| 60 | * entire device. The second level, referred to as the IP level, contains |
| 61 | * registers which are specific to the IP of the device. The two levels of |
| 62 | * registers are designed to be hierarchical such that the device level is |
| 63 | * is a more general register set above the more specific registers of the IP. |
| 64 | * The IP level of registers provides functionality which is typically common |
| 65 | * across all devices and allows IP designers to focus on the unique aspects |
| 66 | * of the IP. |
| 67 | * |
| 68 | * Critical Sections |
| 69 | * |
| 70 | * It is the responsibility of the device driver designer to use critical |
| 71 | * sections as necessary when calling functions of the IPIF. This component |
| 72 | * does not use critical sections and it does access registers using |
| 73 | * read-modify-write operations. Calls to IPIF functions from a main thread |
| 74 | * and from an interrupt context could produce unpredictable behavior such that |
| 75 | * the caller must provide the appropriate critical sections. |
| 76 | * |
| 77 | * Mutual Exclusion |
| 78 | * |
| 79 | * The functions of the IPIF are not thread safe such that the caller of all |
| 80 | * functions is responsible for ensuring mutual exclusion for an IPIF. Mutual |
| 81 | * exclusion across multiple IPIF components is not necessary. |
| 82 | * |
| 83 | * NOTES: |
| 84 | * |
| 85 | * None. |
| 86 | * |
| 87 | * MODIFICATION HISTORY: |
| 88 | * |
| 89 | * Ver Who Date Changes |
| 90 | * ----- ---- -------- ----------------------------------------------- |
| 91 | * 1.23b jhl 02/27/01 Repartioned to minimize size |
| 92 | * |
| 93 | ******************************************************************************/ |
| 94 | |
| 95 | #ifndef XIPIF_H /* prevent circular inclusions */ |
| 96 | #define XIPIF_H /* by using protection macros */ |
| 97 | |
| 98 | /***************************** Include Files *********************************/ |
| 99 | #include "xbasic_types.h" |
| 100 | #include "xstatus.h" |
| 101 | #include "xversion.h" |
| 102 | |
| 103 | /************************** Constant Definitions *****************************/ |
| 104 | |
| 105 | /* the following constants define the register offsets for the registers of the |
| 106 | * IPIF, there are some holes in the memory map for reserved addresses to allow |
| 107 | * other registers to be added and still match the memory map of the interrupt |
| 108 | * controller registers |
| 109 | */ |
| 110 | #define XIIF_V123B_DISR_OFFSET 0UL /* device interrupt status register */ |
| 111 | #define XIIF_V123B_DIPR_OFFSET 4UL /* device interrupt pending register */ |
| 112 | #define XIIF_V123B_DIER_OFFSET 8UL /* device interrupt enable register */ |
| 113 | #define XIIF_V123B_DIIR_OFFSET 24UL /* device interrupt ID register */ |
| 114 | #define XIIF_V123B_DGIER_OFFSET 28UL /* device global interrupt enable reg */ |
| 115 | #define XIIF_V123B_IISR_OFFSET 32UL /* IP interrupt status register */ |
| 116 | #define XIIF_V123B_IIER_OFFSET 40UL /* IP interrupt enable register */ |
| 117 | #define XIIF_V123B_RESETR_OFFSET 64UL /* reset register */ |
| 118 | |
| 119 | #define XIIF_V123B_RESET_MASK 0xAUL |
| 120 | |
| 121 | /* the following constant is used for the device global interrupt enable |
| 122 | * register, to enable all interrupts for the device, this is the only bit |
| 123 | * in the register |
| 124 | */ |
| 125 | #define XIIF_V123B_GINTR_ENABLE_MASK 0x80000000UL |
| 126 | |
| 127 | /* the following constants contain the masks to identify each internal IPIF |
| 128 | * condition in the device registers of the IPIF, interrupts are assigned |
| 129 | * in the register from LSB to the MSB |
| 130 | */ |
| 131 | #define XIIF_V123B_ERROR_MASK 1UL /* LSB of the register */ |
| 132 | |
| 133 | /* The following constants contain interrupt IDs which identify each internal |
| 134 | * IPIF condition, this value must correlate with the mask constant for the |
| 135 | * error |
| 136 | */ |
| 137 | #define XIIF_V123B_ERROR_INTERRUPT_ID 0 /* interrupt bit #, (LSB = 0) */ |
| 138 | #define XIIF_V123B_NO_INTERRUPT_ID 128 /* no interrupts are pending */ |
| 139 | |
| 140 | /**************************** Type Definitions *******************************/ |
| 141 | |
| 142 | /***************** Macros (Inline Functions) Definitions *********************/ |
| 143 | |
| 144 | /****************************************************************************** |
| 145 | * |
| 146 | * MACRO: |
| 147 | * |
| 148 | * XIIF_V123B_RESET |
| 149 | * |
| 150 | * DESCRIPTION: |
| 151 | * |
| 152 | * Reset the IPIF component and hardware. This is a destructive operation that |
| 153 | * could cause the loss of data since resetting the IPIF of a device also |
| 154 | * resets the device using the IPIF and any blocks, such as FIFOs or DMA |
| 155 | * channels, within the IPIF. All registers of the IPIF will contain their |
| 156 | * reset value when this function returns. |
| 157 | * |
| 158 | * ARGUMENTS: |
| 159 | * |
| 160 | * RegBaseAddress contains the base address of the IPIF registers. |
| 161 | * |
| 162 | * RETURN VALUE: |
| 163 | * |
| 164 | * None. |
| 165 | * |
| 166 | * NOTES: |
| 167 | * |
| 168 | * None. |
| 169 | * |
| 170 | ******************************************************************************/ |
| 171 | |
| 172 | /* the following constant is used in the reset register to cause the IPIF to |
| 173 | * reset |
| 174 | */ |
| 175 | #define XIIF_V123B_RESET(RegBaseAddress) \ |
| 176 | XIo_Out32(RegBaseAddress + XIIF_V123B_RESETR_OFFSET, XIIF_V123B_RESET_MASK) |
| 177 | |
| 178 | /****************************************************************************** |
| 179 | * |
| 180 | * MACRO: |
| 181 | * |
| 182 | * XIIF_V123B_WRITE_DISR |
| 183 | * |
| 184 | * DESCRIPTION: |
| 185 | * |
| 186 | * This function sets the device interrupt status register to the value. |
| 187 | * This register indicates the status of interrupt sources for a device |
| 188 | * which contains the IPIF. The status is independent of whether interrupts |
| 189 | * are enabled and could be used for polling a device at a higher level rather |
| 190 | * than a more detailed level. |
| 191 | * |
| 192 | * Each bit of the register correlates to a specific interrupt source within the |
| 193 | * device which contains the IPIF. With the exception of some internal IPIF |
| 194 | * conditions, the contents of this register are not latched but indicate |
| 195 | * the live status of the interrupt sources within the device. Writing any of |
| 196 | * the non-latched bits of the register will have no effect on the register. |
| 197 | * |
| 198 | * For the latched bits of this register only, setting a bit which is zero |
| 199 | * within this register causes an interrupt to generated. The device global |
| 200 | * interrupt enable register and the device interrupt enable register must be set |
| 201 | * appropriately to allow an interrupt to be passed out of the device. The |
| 202 | * interrupt is cleared by writing to this register with the bits to be |
| 203 | * cleared set to a one and all others to zero. This register implements a |
| 204 | * toggle on write functionality meaning any bits which are set in the value |
| 205 | * written cause the bits in the register to change to the opposite state. |
| 206 | * |
| 207 | * This function writes the specified value to the register such that |
| 208 | * some bits may be set and others cleared. It is the caller's responsibility |
| 209 | * to get the value of the register prior to setting the value to prevent a |
| 210 | * destructive behavior. |
| 211 | * |
| 212 | * ARGUMENTS: |
| 213 | * |
| 214 | * RegBaseAddress contains the base address of the IPIF registers. |
| 215 | * |
| 216 | * Status contains the value to be written to the interrupt status register of |
| 217 | * the device. The only bits which can be written are the latched bits which |
| 218 | * contain the internal IPIF conditions. The following values may be used to |
| 219 | * set the status register or clear an interrupt condition. |
| 220 | * |
| 221 | * XIIF_V123B_ERROR_MASK Indicates a device error in the IPIF |
| 222 | * |
| 223 | * RETURN VALUE: |
| 224 | * |
| 225 | * None. |
| 226 | * |
| 227 | * NOTES: |
| 228 | * |
| 229 | * None. |
| 230 | * |
| 231 | ******************************************************************************/ |
| 232 | #define XIIF_V123B_WRITE_DISR(RegBaseAddress, Status) \ |
| 233 | XIo_Out32((RegBaseAddress) + XIIF_V123B_DISR_OFFSET, (Status)) |
| 234 | |
| 235 | /****************************************************************************** |
| 236 | * |
| 237 | * MACRO: |
| 238 | * |
| 239 | * XIIF_V123B_READ_DISR |
| 240 | * |
| 241 | * DESCRIPTION: |
| 242 | * |
| 243 | * This function gets the device interrupt status register contents. |
| 244 | * This register indicates the status of interrupt sources for a device |
| 245 | * which contains the IPIF. The status is independent of whether interrupts |
| 246 | * are enabled and could be used for polling a device at a higher level. |
| 247 | * |
| 248 | * Each bit of the register correlates to a specific interrupt source within the |
| 249 | * device which contains the IPIF. With the exception of some internal IPIF |
| 250 | * conditions, the contents of this register are not latched but indicate |
| 251 | * the live status of the interrupt sources within the device. |
| 252 | * |
| 253 | * For only the latched bits of this register, the interrupt may be cleared by |
| 254 | * writing to these bits in the status register. |
| 255 | * |
| 256 | * ARGUMENTS: |
| 257 | * |
| 258 | * RegBaseAddress contains the base address of the IPIF registers. |
| 259 | * |
| 260 | * RETURN VALUE: |
| 261 | * |
| 262 | * A status which contains the value read from the interrupt status register of |
| 263 | * the device. The bit definitions are specific to the device with |
| 264 | * the exception of the latched internal IPIF condition bits. The following |
| 265 | * values may be used to detect internal IPIF conditions in the status. |
| 266 | * |
| 267 | * XIIF_V123B_ERROR_MASK Indicates a device error in the IPIF |
| 268 | * |
| 269 | * NOTES: |
| 270 | * |
| 271 | * None. |
| 272 | * |
| 273 | ******************************************************************************/ |
| 274 | #define XIIF_V123B_READ_DISR(RegBaseAddress) \ |
| 275 | XIo_In32((RegBaseAddress) + XIIF_V123B_DISR_OFFSET) |
| 276 | |
| 277 | /****************************************************************************** |
| 278 | * |
| 279 | * MACRO: |
| 280 | * |
| 281 | * XIIF_V123B_WRITE_DIER |
| 282 | * |
| 283 | * DESCRIPTION: |
| 284 | * |
| 285 | * This function sets the device interrupt enable register contents. |
| 286 | * This register controls which interrupt sources of the device are allowed to |
| 287 | * generate an interrupt. The device global interrupt enable register must also |
| 288 | * be set appropriately for an interrupt to be passed out of the device. |
| 289 | * |
| 290 | * Each bit of the register correlates to a specific interrupt source within the |
| 291 | * device which contains the IPIF. Setting a bit in this register enables that |
| 292 | * interrupt source to generate an interrupt. Clearing a bit in this register |
| 293 | * disables interrupt generation for that interrupt source. |
| 294 | * |
| 295 | * This function writes only the specified value to the register such that |
| 296 | * some interrupts source may be enabled and others disabled. It is the |
| 297 | * caller's responsibility to get the value of the interrupt enable register |
| 298 | * prior to setting the value to prevent an destructive behavior. |
| 299 | * |
| 300 | * An interrupt source may not be enabled to generate an interrupt, but can |
| 301 | * still be polled in the interrupt status register. |
| 302 | * |
| 303 | * ARGUMENTS: |
| 304 | * |
| 305 | * RegBaseAddress contains the base address of the IPIF registers. |
| 306 | * |
| 307 | * Enable contains the value to be written to the interrupt enable register |
| 308 | * of the device. The bit definitions are specific to the device with |
| 309 | * the exception of the internal IPIF conditions. The following |
| 310 | * values may be used to enable the internal IPIF conditions interrupts. |
| 311 | * |
| 312 | * XIIF_V123B_ERROR_MASK Indicates a device error in the IPIF |
| 313 | * |
| 314 | * RETURN VALUE: |
| 315 | * |
| 316 | * None. |
| 317 | * |
| 318 | * NOTES: |
| 319 | * |
| 320 | * Signature: u32 XIIF_V123B_WRITE_DIER(u32 RegBaseAddress, |
| 321 | * u32 Enable) |
| 322 | * |
| 323 | ******************************************************************************/ |
| 324 | #define XIIF_V123B_WRITE_DIER(RegBaseAddress, Enable) \ |
| 325 | XIo_Out32((RegBaseAddress) + XIIF_V123B_DIER_OFFSET, (Enable)) |
| 326 | |
| 327 | /****************************************************************************** |
| 328 | * |
| 329 | * MACRO: |
| 330 | * |
| 331 | * XIIF_V123B_READ_DIER |
| 332 | * |
| 333 | * DESCRIPTION: |
| 334 | * |
| 335 | * This function gets the device interrupt enable register contents. |
| 336 | * This register controls which interrupt sources of the device |
| 337 | * are allowed to generate an interrupt. The device global interrupt enable |
| 338 | * register and the device interrupt enable register must also be set |
| 339 | * appropriately for an interrupt to be passed out of the device. |
| 340 | * |
| 341 | * Each bit of the register correlates to a specific interrupt source within the |
| 342 | * device which contains the IPIF. Setting a bit in this register enables that |
| 343 | * interrupt source to generate an interrupt if the global enable is set |
| 344 | * appropriately. Clearing a bit in this register disables interrupt generation |
| 345 | * for that interrupt source regardless of the global interrupt enable. |
| 346 | * |
| 347 | * ARGUMENTS: |
| 348 | * |
| 349 | * RegBaseAddress contains the base address of the IPIF registers. |
| 350 | * |
| 351 | * RETURN VALUE: |
| 352 | * |
| 353 | * The value read from the interrupt enable register of the device. The bit |
| 354 | * definitions are specific to the device with the exception of the internal |
| 355 | * IPIF conditions. The following values may be used to determine from the |
| 356 | * value if the internal IPIF conditions interrupts are enabled. |
| 357 | * |
| 358 | * XIIF_V123B_ERROR_MASK Indicates a device error in the IPIF |
| 359 | * |
| 360 | * NOTES: |
| 361 | * |
| 362 | * None. |
| 363 | * |
| 364 | ******************************************************************************/ |
| 365 | #define XIIF_V123B_READ_DIER(RegBaseAddress) \ |
| 366 | XIo_In32((RegBaseAddress) + XIIF_V123B_DIER_OFFSET) |
| 367 | |
| 368 | /****************************************************************************** |
| 369 | * |
| 370 | * MACRO: |
| 371 | * |
| 372 | * XIIF_V123B_READ_DIPR |
| 373 | * |
| 374 | * DESCRIPTION: |
| 375 | * |
| 376 | * This function gets the device interrupt pending register contents. |
| 377 | * This register indicates the pending interrupt sources, those that are waiting |
| 378 | * to be serviced by the software, for a device which contains the IPIF. |
| 379 | * An interrupt must be enabled in the interrupt enable register of the IPIF to |
| 380 | * be pending. |
| 381 | * |
| 382 | * Each bit of the register correlates to a specific interrupt source within the |
| 383 | * the device which contains the IPIF. With the exception of some internal IPIF |
| 384 | * conditions, the contents of this register are not latched since the condition |
| 385 | * is latched in the IP interrupt status register, by an internal block of the |
| 386 | * IPIF such as a FIFO or DMA channel, or by the IP of the device. This register |
| 387 | * is read only and is not latched, but it is necessary to acknowledge (clear) |
| 388 | * the interrupt condition by performing the appropriate processing for the IP |
| 389 | * or block within the IPIF. |
| 390 | * |
| 391 | * This register can be thought of as the contents of the interrupt status |
| 392 | * register ANDed with the contents of the interrupt enable register. |
| 393 | * |
| 394 | * ARGUMENTS: |
| 395 | * |
| 396 | * RegBaseAddress contains the base address of the IPIF registers. |
| 397 | * |
| 398 | * RETURN VALUE: |
| 399 | * |
| 400 | * The value read from the interrupt pending register of the device. The bit |
| 401 | * definitions are specific to the device with the exception of the latched |
| 402 | * internal IPIF condition bits. The following values may be used to detect |
| 403 | * internal IPIF conditions in the value. |
| 404 | * |
| 405 | * XIIF_V123B_ERROR_MASK Indicates a device error in the IPIF |
| 406 | * |
| 407 | * NOTES: |
| 408 | * |
| 409 | * None. |
| 410 | * |
| 411 | ******************************************************************************/ |
| 412 | #define XIIF_V123B_READ_DIPR(RegBaseAddress) \ |
| 413 | XIo_In32((RegBaseAddress) + XIIF_V123B_DIPR_OFFSET) |
| 414 | |
| 415 | /****************************************************************************** |
| 416 | * |
| 417 | * MACRO: |
| 418 | * |
| 419 | * XIIF_V123B_READ_DIIR |
| 420 | * |
| 421 | * DESCRIPTION: |
| 422 | * |
| 423 | * This function gets the device interrupt ID for the highest priority interrupt |
| 424 | * which is pending from the interrupt ID register. This function provides |
| 425 | * priority resolution such that faster interrupt processing is possible. |
| 426 | * Without priority resolution, it is necessary for the software to read the |
| 427 | * interrupt pending register and then check each interrupt source to determine |
| 428 | * if an interrupt is pending. Priority resolution becomes more important as the |
| 429 | * number of interrupt sources becomes larger. |
| 430 | * |
| 431 | * Interrupt priorities are based upon the bit position of the interrupt in the |
| 432 | * interrupt pending register with bit 0 being the highest priority. The |
| 433 | * interrupt ID is the priority of the interrupt, 0 - 31, with 0 being the |
| 434 | * highest priority. The interrupt ID register is live rather than latched such |
| 435 | * that multiple calls to this function may not yield the same results. A |
| 436 | * special value, outside of the interrupt priority range of 0 - 31, is |
| 437 | * contained in the register which indicates that no interrupt is pending. This |
| 438 | * may be useful for allowing software to continue processing interrupts in a |
| 439 | * loop until there are no longer any interrupts pending. |
| 440 | * |
| 441 | * The interrupt ID is designed to allow a function pointer table to be used |
| 442 | * in the software such that the interrupt ID is used as an index into that |
| 443 | * table. The function pointer table could contain an instance pointer, such |
| 444 | * as to DMA channel, and a function pointer to the function which handles |
| 445 | * that interrupt. This design requires the interrupt processing of the device |
| 446 | * driver to be partitioned into smaller more granular pieces based upon |
| 447 | * hardware used by the device, such as DMA channels and FIFOs. |
| 448 | * |
| 449 | * It is not mandatory that this function be used by the device driver software. |
| 450 | * It may choose to read the pending register and resolve the pending interrupt |
| 451 | * priorities on it's own. |
| 452 | * |
| 453 | * ARGUMENTS: |
| 454 | * |
| 455 | * RegBaseAddress contains the base address of the IPIF registers. |
| 456 | * |
| 457 | * RETURN VALUE: |
| 458 | * |
| 459 | * An interrupt ID, 0 - 31, which identifies the highest priority interrupt |
| 460 | * which is pending. A value of XIIF_NO_INTERRUPT_ID indicates that there is |
| 461 | * no interrupt pending. The following values may be used to identify the |
| 462 | * interrupt ID for the internal IPIF interrupts. |
| 463 | * |
| 464 | * XIIF_V123B_ERROR_INTERRUPT_ID Indicates a device error in the IPIF |
| 465 | * |
| 466 | * NOTES: |
| 467 | * |
| 468 | * None. |
| 469 | * |
| 470 | ******************************************************************************/ |
| 471 | #define XIIF_V123B_READ_DIIR(RegBaseAddress) \ |
| 472 | XIo_In32((RegBaseAddress) + XIIF_V123B_DIIR_OFFSET) |
| 473 | |
| 474 | /****************************************************************************** |
| 475 | * |
| 476 | * MACRO: |
| 477 | * |
| 478 | * XIIF_V123B_GLOBAL_INTR_DISABLE |
| 479 | * |
| 480 | * DESCRIPTION: |
| 481 | * |
| 482 | * This function disables all interrupts for the device by writing to the global |
| 483 | * interrupt enable register. This register provides the ability to disable |
| 484 | * interrupts without any modifications to the interrupt enable register such |
| 485 | * that it is minimal effort to restore the interrupts to the previous enabled |
| 486 | * state. The corresponding function, XIpIf_GlobalIntrEnable, is provided to |
| 487 | * restore the interrupts to the previous enabled state. This function is |
| 488 | * designed to be used in critical sections of device drivers such that it is |
| 489 | * not necessary to disable other device interrupts. |
| 490 | * |
| 491 | * ARGUMENTS: |
| 492 | * |
| 493 | * RegBaseAddress contains the base address of the IPIF registers. |
| 494 | * |
| 495 | * RETURN VALUE: |
| 496 | * |
| 497 | * None. |
| 498 | * |
| 499 | * NOTES: |
| 500 | * |
| 501 | * None. |
| 502 | * |
| 503 | ******************************************************************************/ |
| 504 | #define XIIF_V123B_GINTR_DISABLE(RegBaseAddress) \ |
| 505 | XIo_Out32((RegBaseAddress) + XIIF_V123B_DGIER_OFFSET, 0) |
| 506 | |
| 507 | /****************************************************************************** |
| 508 | * |
| 509 | * MACRO: |
| 510 | * |
| 511 | * XIIF_V123B_GINTR_ENABLE |
| 512 | * |
| 513 | * DESCRIPTION: |
| 514 | * |
| 515 | * This function writes to the global interrupt enable register to enable |
| 516 | * interrupts from the device. This register provides the ability to enable |
| 517 | * interrupts without any modifications to the interrupt enable register such |
| 518 | * that it is minimal effort to restore the interrupts to the previous enabled |
| 519 | * state. This function does not enable individual interrupts as the interrupt |
| 520 | * enable register must be set appropriately. This function is designed to be |
| 521 | * used in critical sections of device drivers such that it is not necessary to |
| 522 | * disable other device interrupts. |
| 523 | * |
| 524 | * ARGUMENTS: |
| 525 | * |
| 526 | * RegBaseAddress contains the base address of the IPIF registers. |
| 527 | * |
| 528 | * RETURN VALUE: |
| 529 | * |
| 530 | * None. |
| 531 | * |
| 532 | * NOTES: |
| 533 | * |
| 534 | * None. |
| 535 | * |
| 536 | ******************************************************************************/ |
| 537 | #define XIIF_V123B_GINTR_ENABLE(RegBaseAddress) \ |
| 538 | XIo_Out32((RegBaseAddress) + XIIF_V123B_DGIER_OFFSET, \ |
| 539 | XIIF_V123B_GINTR_ENABLE_MASK) |
| 540 | |
| 541 | /****************************************************************************** |
| 542 | * |
| 543 | * MACRO: |
| 544 | * |
| 545 | * XIIF_V123B_IS_GINTR_ENABLED |
| 546 | * |
| 547 | * DESCRIPTION: |
| 548 | * |
| 549 | * This function determines if interrupts are enabled at the global level by |
| 550 | * reading the gloabl interrupt register. This register provides the ability to |
| 551 | * disable interrupts without any modifications to the interrupt enable register |
| 552 | * such that it is minimal effort to restore the interrupts to the previous |
| 553 | * enabled state. |
| 554 | * |
| 555 | * ARGUMENTS: |
| 556 | * |
| 557 | * RegBaseAddress contains the base address of the IPIF registers. |
| 558 | * |
| 559 | * RETURN VALUE: |
| 560 | * |
wdenk | 97e8bda | 2004-09-29 22:43:59 +0000 | [diff] [blame] | 561 | * XTRUE if interrupts are enabled for the IPIF, XFALSE otherwise. |
wdenk | e537b3b | 2004-02-23 23:54:43 +0000 | [diff] [blame] | 562 | * |
| 563 | * NOTES: |
| 564 | * |
| 565 | * None. |
| 566 | * |
| 567 | ******************************************************************************/ |
| 568 | #define XIIF_V123B_IS_GINTR_ENABLED(RegBaseAddress) \ |
| 569 | (XIo_In32((RegBaseAddress) + XIIF_V123B_DGIER_OFFSET) == \ |
| 570 | XIIF_V123B_GINTR_ENABLE_MASK) |
| 571 | |
| 572 | /****************************************************************************** |
| 573 | * |
| 574 | * MACRO: |
| 575 | * |
| 576 | * XIIF_V123B_WRITE_IISR |
| 577 | * |
| 578 | * DESCRIPTION: |
| 579 | * |
| 580 | * This function sets the IP interrupt status register to the specified value. |
| 581 | * This register indicates the status of interrupt sources for the IP of the |
| 582 | * device. The IP is defined as the part of the device that connects to the |
| 583 | * IPIF. The status is independent of whether interrupts are enabled such that |
| 584 | * the status register may also be polled when interrupts are not enabled. |
| 585 | * |
| 586 | * Each bit of the register correlates to a specific interrupt source within the |
| 587 | * IP. All bits of this register are latched. Setting a bit which is zero |
| 588 | * within this register causes an interrupt to be generated. The device global |
| 589 | * interrupt enable register and the device interrupt enable register must be set |
| 590 | * appropriately to allow an interrupt to be passed out of the device. The |
| 591 | * interrupt is cleared by writing to this register with the bits to be |
| 592 | * cleared set to a one and all others to zero. This register implements a |
| 593 | * toggle on write functionality meaning any bits which are set in the value |
| 594 | * written cause the bits in the register to change to the opposite state. |
| 595 | * |
| 596 | * This function writes only the specified value to the register such that |
| 597 | * some status bits may be set and others cleared. It is the caller's |
| 598 | * responsibility to get the value of the register prior to setting the value |
| 599 | * to prevent an destructive behavior. |
| 600 | * |
| 601 | * ARGUMENTS: |
| 602 | * |
| 603 | * RegBaseAddress contains the base address of the IPIF registers. |
| 604 | * |
| 605 | * Status contains the value to be written to the IP interrupt status |
| 606 | * register. The bit definitions are specific to the device IP. |
| 607 | * |
| 608 | * RETURN VALUE: |
| 609 | * |
| 610 | * None. |
| 611 | * |
| 612 | * NOTES: |
| 613 | * |
| 614 | * None. |
| 615 | * |
| 616 | ******************************************************************************/ |
| 617 | #define XIIF_V123B_WRITE_IISR(RegBaseAddress, Status) \ |
| 618 | XIo_Out32((RegBaseAddress) + XIIF_V123B_IISR_OFFSET, (Status)) |
| 619 | |
| 620 | /****************************************************************************** |
| 621 | * |
| 622 | * MACRO: |
| 623 | * |
| 624 | * XIIF_V123B_READ_IISR |
| 625 | * |
| 626 | * DESCRIPTION: |
| 627 | * |
| 628 | * This function gets the contents of the IP interrupt status register. |
| 629 | * This register indicates the status of interrupt sources for the IP of the |
| 630 | * device. The IP is defined as the part of the device that connects to the |
| 631 | * IPIF. The status is independent of whether interrupts are enabled such |
| 632 | * that the status register may also be polled when interrupts are not enabled. |
| 633 | * |
| 634 | * Each bit of the register correlates to a specific interrupt source within the |
| 635 | * device. All bits of this register are latched. Writing a 1 to a bit within |
| 636 | * this register causes an interrupt to be generated if enabled in the interrupt |
| 637 | * enable register and the global interrupt enable is set. Since the status is |
| 638 | * latched, each status bit must be acknowledged in order for the bit in the |
| 639 | * status register to be updated. Each bit can be acknowledged by writing a |
| 640 | * 0 to the bit in the status register. |
| 641 | |
| 642 | * ARGUMENTS: |
| 643 | * |
| 644 | * RegBaseAddress contains the base address of the IPIF registers. |
| 645 | * |
| 646 | * RETURN VALUE: |
| 647 | * |
| 648 | * A status which contains the value read from the IP interrupt status register. |
| 649 | * The bit definitions are specific to the device IP. |
| 650 | * |
| 651 | * NOTES: |
| 652 | * |
| 653 | * None. |
| 654 | * |
| 655 | ******************************************************************************/ |
| 656 | #define XIIF_V123B_READ_IISR(RegBaseAddress) \ |
| 657 | XIo_In32((RegBaseAddress) + XIIF_V123B_IISR_OFFSET) |
| 658 | |
| 659 | /****************************************************************************** |
| 660 | * |
| 661 | * MACRO: |
| 662 | * |
| 663 | * XIIF_V123B_WRITE_IIER |
| 664 | * |
| 665 | * DESCRIPTION: |
| 666 | * |
| 667 | * This function sets the IP interrupt enable register contents. This register |
| 668 | * controls which interrupt sources of the IP are allowed to generate an |
| 669 | * interrupt. The global interrupt enable register and the device interrupt |
| 670 | * enable register must also be set appropriately for an interrupt to be |
| 671 | * passed out of the device containing the IPIF and the IP. |
| 672 | * |
| 673 | * Each bit of the register correlates to a specific interrupt source within the |
| 674 | * IP. Setting a bit in this register enables the interrupt source to generate |
| 675 | * an interrupt. Clearing a bit in this register disables interrupt generation |
| 676 | * for that interrupt source. |
| 677 | * |
| 678 | * This function writes only the specified value to the register such that |
| 679 | * some interrupt sources may be enabled and others disabled. It is the |
| 680 | * caller's responsibility to get the value of the interrupt enable register |
| 681 | * prior to setting the value to prevent an destructive behavior. |
| 682 | * |
| 683 | * ARGUMENTS: |
| 684 | * |
| 685 | * RegBaseAddress contains the base address of the IPIF registers. |
| 686 | * |
| 687 | * Enable contains the value to be written to the IP interrupt enable register. |
| 688 | * The bit definitions are specific to the device IP. |
| 689 | * |
| 690 | * RETURN VALUE: |
| 691 | * |
| 692 | * None. |
| 693 | * |
| 694 | * NOTES: |
| 695 | * |
| 696 | * None. |
| 697 | * |
| 698 | ******************************************************************************/ |
| 699 | #define XIIF_V123B_WRITE_IIER(RegBaseAddress, Enable) \ |
| 700 | XIo_Out32((RegBaseAddress) + XIIF_V123B_IIER_OFFSET, (Enable)) |
| 701 | |
| 702 | /****************************************************************************** |
| 703 | * |
| 704 | * MACRO: |
| 705 | * |
| 706 | * XIIF_V123B_READ_IIER |
| 707 | * |
| 708 | * DESCRIPTION: |
| 709 | * |
| 710 | * |
| 711 | * This function gets the IP interrupt enable register contents. This register |
| 712 | * controls which interrupt sources of the IP are allowed to generate an |
| 713 | * interrupt. The global interrupt enable register and the device interrupt |
| 714 | * enable register must also be set appropriately for an interrupt to be |
| 715 | * passed out of the device containing the IPIF and the IP. |
| 716 | * |
| 717 | * Each bit of the register correlates to a specific interrupt source within the |
| 718 | * IP. Setting a bit in this register enables the interrupt source to generate |
| 719 | * an interrupt. Clearing a bit in this register disables interrupt generation |
| 720 | * for that interrupt source. |
| 721 | * |
| 722 | * ARGUMENTS: |
| 723 | * |
| 724 | * RegBaseAddress contains the base address of the IPIF registers. |
| 725 | * |
| 726 | * RETURN VALUE: |
| 727 | * |
| 728 | * The contents read from the IP interrupt enable register. The bit definitions |
| 729 | * are specific to the device IP. |
| 730 | * |
| 731 | * NOTES: |
| 732 | * |
| 733 | * Signature: u32 XIIF_V123B_READ_IIER(u32 RegBaseAddress) |
| 734 | * |
| 735 | ******************************************************************************/ |
| 736 | #define XIIF_V123B_READ_IIER(RegBaseAddress) \ |
| 737 | XIo_In32((RegBaseAddress) + XIIF_V123B_IIER_OFFSET) |
| 738 | |
| 739 | /************************** Function Prototypes ******************************/ |
| 740 | |
| 741 | /* |
| 742 | * Initialization Functions |
| 743 | */ |
| 744 | XStatus XIpIfV123b_SelfTest(u32 RegBaseAddress, u8 IpRegistersWidth); |
| 745 | |
| 746 | #endif /* end of protection macro */ |