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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Marcel Ziswiler90392d02016-11-14 21:40:26 +01002/*
3 * Copyright (c) 2016 Marcel Ziswiler <marcel.ziswiler@toradex.com>
Marcel Ziswiler90392d02016-11-14 21:40:26 +01004 */
5
6#ifndef __SERIAL_PXA_H
7#define __SERIAL_PXA_H
8
9/*
10 * The numbering scheme differs here for PXA25x, PXA27x and PXA3xx so we can
11 * easily handle enabling of clock.
12 */
13#ifdef CONFIG_CPU_MONAHANS
14#define UART_CLK_BASE CKENA_21_BTUART
15#define UART_CLK_REG CKENA
16#define BTUART_INDEX 0
17#define FFUART_INDEX 1
18#define STUART_INDEX 2
Marcel Ziswiler90392d02016-11-14 21:40:26 +010019#else /* PXA27x */
20#define UART_CLK_BASE CKEN5_STUART
21#define UART_CLK_REG CKEN
22#define STUART_INDEX 0
23#define FFUART_INDEX 1
24#define BTUART_INDEX 2
25#endif
26
27/*
Simon Glassb75b15b2020-12-03 16:55:23 -070028 * struct pxa_serial_plat - information about a PXA port
Marcel Ziswiler90392d02016-11-14 21:40:26 +010029 *
Marcel Ziswiler92f24782019-05-20 02:44:55 +020030 * @base: Uart port base register address
31 * @port: Uart port index, for cpu with pinmux for uart / gpio
32 * baudrtatre: Uart port baudrate
Marcel Ziswiler90392d02016-11-14 21:40:26 +010033 */
Simon Glassb75b15b2020-12-03 16:55:23 -070034struct pxa_serial_plat {
Marcel Ziswiler90392d02016-11-14 21:40:26 +010035 struct pxa_uart_regs *base;
36 int port;
37 int baudrate;
38};
39
40#endif /* __SERIAL_PXA_H */