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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Heiko Schocher44a93442015-06-29 09:10:48 +02002/*
3 * (C) Copyright 2007-2008
4 * Stelian Pop <stelian@popies.net>
5 * Lead Tech Design <www.leadtechdesign.com>
6 *
7 * (C) Copyright 2010
8 * Achim Ehrlich <aehrlich@taskit.de>
9 * taskit GmbH <www.taskit.de>
10 *
11 * (C) Copyright 2012
12 * Markus Hubig <mhubig@imko.de>
13 * IMKO GmbH <www.imko.de>
14 *
15 * (C) Copyright 2014
16 * Heiko Schocher <hs@denx.de>
17 * DENX Software Engineering GmbH
18 *
19 * Configuation settings for the smartweb.
Heiko Schocher44a93442015-06-29 09:10:48 +020020 */
21
22#ifndef __CONFIG_H
23#define __CONFIG_H
24
25/*
26 * SoC must be defined first, before hardware.h is included.
27 * In this case SoC is defined in boards.cfg.
28 */
29#include <asm/hardware.h>
Heiko Schochercf5137c2015-09-08 11:52:52 +020030#include <linux/sizes.h>
Heiko Schocher44a93442015-06-29 09:10:48 +020031
32/*
33 * Warning: changing CONFIG_SYS_TEXT_BASE requires adapting the initial boot
34 * program. Since the linker has to swallow that define, we must use a pure
35 * hex number here!
36 */
Heiko Schocher44a93442015-06-29 09:10:48 +020037
38/* ARM asynchronous clock */
39#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
40#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432MHz crystal */
41
42/* misc settings */
Heiko Schocher44a93442015-06-29 09:10:48 +020043
44/* setting board specific options */
Matthias Michel0ae5e922016-01-27 15:56:07 +010045#define CONFIG_SYS_AUTOLOAD "yes"
Heiko Schocher44a93442015-06-29 09:10:48 +020046
Heiko Schocher44a93442015-06-29 09:10:48 +020047/*
48 * SDRAM: 1 bank, 64 MB, base address 0x20000000
49 * Already initialized before u-boot gets started.
50 */
Heiko Schocher44a93442015-06-29 09:10:48 +020051#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1
Heiko Schochercf5137c2015-09-08 11:52:52 +020052#define CONFIG_SYS_SDRAM_SIZE (64 * SZ_1M)
Heiko Schocher44a93442015-06-29 09:10:48 +020053
54/*
55 * Perform a SDRAM Memtest from the start of SDRAM
56 * till the beginning of the U-Boot position in RAM.
57 */
Heiko Schocher44a93442015-06-29 09:10:48 +020058
Heiko Schocher44a93442015-06-29 09:10:48 +020059/* NAND flash settings */
Heiko Schocher44a93442015-06-29 09:10:48 +020060#define CONFIG_SYS_MAX_NAND_DEVICE 1
61#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
62#define CONFIG_SYS_NAND_DBW_8
63#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
64#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
65#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
66#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC13
67
Heiko Schocher44a93442015-06-29 09:10:48 +020068/* serial console */
Heiko Schocher44a93442015-06-29 09:10:48 +020069#define CONFIG_USART_BASE ATMEL_BASE_DBGU
70#define CONFIG_USART_ID ATMEL_ID_SYS
Heiko Schocher44a93442015-06-29 09:10:48 +020071
Heiko Schocher44a93442015-06-29 09:10:48 +020072#if !defined(CONFIG_SPL_BUILD)
73/* USB configuration */
74#define CONFIG_USB_ATMEL
75#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
76#define CONFIG_USB_OHCI_NEW
Heiko Schocher44a93442015-06-29 09:10:48 +020077#define CONFIG_SYS_USB_OHCI_CPU_INIT
78#define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_UHP_BASE
79#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9260"
80#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
Heiko Schochercf5137c2015-09-08 11:52:52 +020081
Heiko Schochercf5137c2015-09-08 11:52:52 +020082/* USB DFU support */
Heiko Schochercf5137c2015-09-08 11:52:52 +020083
Heiko Schochercf5137c2015-09-08 11:52:52 +020084#define CONFIG_USB_GADGET_AT91
85
86/* DFU class support */
Heiko Schochercf5137c2015-09-08 11:52:52 +020087#define DFU_MANIFEST_POLL_TIMEOUT 25000
Heiko Schocher44a93442015-06-29 09:10:48 +020088#endif
89
90/* General Boot Parameter */
Heiko Schocher44a93442015-06-29 09:10:48 +020091
92/*
Heiko Schocher44a93442015-06-29 09:10:48 +020093 * The NAND Flash partitions:
94 */
Heiko Schochercf5137c2015-09-08 11:52:52 +020095#define CONFIG_ENV_RANGE (SZ_512K)
Heiko Schocher44a93442015-06-29 09:10:48 +020096
97/*
98 * Predefined environment variables.
99 * Usefull to define some easy to use boot commands.
100 */
101#define CONFIG_EXTRA_ENV_SETTINGS \
102 \
103 "basicargs=console=ttyS0,115200\0" \
104 \
Tom Rini5ad8e112017-10-22 17:55:07 -0400105 "mtdparts="CONFIG_MTDPARTS_DEFAULT"\0"
Heiko Schocher44a93442015-06-29 09:10:48 +0200106
Heiko Schocher44a93442015-06-29 09:10:48 +0200107/*
108 * Initial stack pointer: 4k - GENERATED_GBL_DATA_SIZE in internal SRAM,
109 * leaving the correct space for initial global data structure above that
110 * address while providing maximum stack area below.
111 */
Tom Rini4ddbade2022-05-25 12:16:03 -0400112#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
113#define CONFIG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM1
Heiko Schocher44a93442015-06-29 09:10:48 +0200114
Heiko Schocher44a93442015-06-29 09:10:48 +0200115/* Defines for SPL */
Heiko Schocher44a93442015-06-29 09:10:48 +0200116
Heiko Schocher44a93442015-06-29 09:10:48 +0200117#define CONFIG_SYS_NAND_ENABLE_PIN_SPL (2*32 + 14)
Heiko Schochercf5137c2015-09-08 11:52:52 +0200118#define CONFIG_SYS_NAND_U_BOOT_SIZE SZ_512K
Heiko Schocher44a93442015-06-29 09:10:48 +0200119#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
120#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
Heiko Schocher44a93442015-06-29 09:10:48 +0200121
Heiko Schochercf5137c2015-09-08 11:52:52 +0200122#define CONFIG_SYS_NAND_SIZE (SZ_256M)
Heiko Schocher44a93442015-06-29 09:10:48 +0200123#define CONFIG_SYS_NAND_ECCSIZE 256
124#define CONFIG_SYS_NAND_ECCBYTES 3
Heiko Schocher44a93442015-06-29 09:10:48 +0200125#define CONFIG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \
126 48, 49, 50, 51, 52, 53, 54, 55, \
127 56, 57, 58, 59, 60, 61, 62, 63, }
128
Heiko Schocher44a93442015-06-29 09:10:48 +0200129#define CONFIG_SYS_MASTER_CLOCK (198656000/2)
130#define AT91_PLL_LOCK_TIMEOUT 1000000
131#define CONFIG_SYS_AT91_PLLA 0x2060bf09
132#define CONFIG_SYS_MCKR 0x100
133#define CONFIG_SYS_MCKR_CSS (0x02 | CONFIG_SYS_MCKR)
134#define CONFIG_SYS_AT91_PLLB 0x10483f0e
135
Heiko Schocher44a93442015-06-29 09:10:48 +0200136#endif /* __CONFIG_H */