blob: 41e0d18f88c6beca860d5400fb763835114fb818 [file] [log] [blame]
Johan Jonkera289fc72022-04-16 17:09:47 +02001/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * (C) Copyright 2015 Google, Inc
4 */
5
6#ifndef __CONFIG_RK3066_COMMON_H
7#define __CONFIG_RK3066_COMMON_H
8
9#include <asm/arch-rockchip/hardware.h>
10#include "rockchip-common.h"
11
Johan Jonkera289fc72022-04-16 17:09:47 +020012#define CONFIG_IRAM_BASE 0x10080000
13
Johan Jonkera289fc72022-04-16 17:09:47 +020014#define CONFIG_SYS_SDRAM_BASE 0x60000000
15#define SDRAM_BANK_SIZE (1024UL << 20UL)
16#define SDRAM_MAX_SIZE CONFIG_NR_DRAM_BANKS * SDRAM_BANK_SIZE
17
18#ifndef CONFIG_SPL_BUILD
19
20#define ENV_MEM_LAYOUT_SETTINGS \
21 "scriptaddr=0x60000000\0" \
22 "pxefile_addr_r=0x60100000\0" \
23 "fdt_addr_r=0x61f00000\0" \
24 "kernel_addr_r=0x62000000\0" \
25 "ramdisk_addr_r=0x64000000\0"
26
27#include <config_distro_bootcmd.h>
28
29#define CONFIG_EXTRA_ENV_SETTINGS \
30 "fdt_high=0x6fffffff\0" \
31 "initrd_high=0x6fffffff\0" \
32 "partitions=" PARTS_DEFAULT \
33 ENV_MEM_LAYOUT_SETTINGS \
34 ROCKCHIP_DEVICE_SETTINGS \
35 BOOTENV
36
37#endif /* CONFIG_SPL_BUILD */
38
39#endif