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Dzmitry Sankouski0061b6f2021-10-17 13:45:41 +03001/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Configuration settings for the EXYNOS 78x0 based boards.
4 *
5 * Copyright (c) 2020 Dzmitry Sankouski (dsankouski@gmail.com)
6 * based on include/exynos7420-common.h
7 * Copyright (C) 2016 Samsung Electronics
8 * Thomas Abraham <thomas.ab@samsung.com>
9 */
10
11#ifndef __CONFIG_EXYNOS78x0_COMMON_H
12#define __CONFIG_EXYNOS78x0_COMMON_H
13
14/* High Level Configuration Options */
15#define CONFIG_SAMSUNG /* in a SAMSUNG core */
16#define CONFIG_S5P
17
18#include <asm/arch/cpu.h> /* get chip and board defs */
19#include <linux/sizes.h>
20
21/* Miscellaneous configurable options */
Dzmitry Sankouski0061b6f2021-10-17 13:45:41 +030022
Dzmitry Sankouski0061b6f2021-10-17 13:45:41 +030023#define CPU_RELEASE_ADDR secondary_boot_addr
24
25#define CONFIG_SYS_BAUDRATE_TABLE \
26 {9600, 19200, 38400, 57600, 115200, 230400, 460800, 921600}
27
Dzmitry Sankouski0061b6f2021-10-17 13:45:41 +030028#define CONFIG_SYS_SDRAM_BASE 0x40000000
Dzmitry Sankouski24e80782022-02-22 21:49:54 +030029#define CONFIG_SYS_BOOTM_LEN SZ_32M
Dzmitry Sankouski0061b6f2021-10-17 13:45:41 +030030/* DRAM Memory Banks */
31#define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */
32#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
33#define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE
34#define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
35#define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE
36#define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
37#define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE
38#define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
39#define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE
40#define PHYS_SDRAM_5 (CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE))
41#define PHYS_SDRAM_5_SIZE SDRAM_BANK_SIZE
42#define PHYS_SDRAM_6 (CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE))
43#define PHYS_SDRAM_6_SIZE SDRAM_BANK_SIZE
44#define PHYS_SDRAM_7 (CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE))
45#define PHYS_SDRAM_7_SIZE SDRAM_BANK_SIZE
46#define PHYS_SDRAM_8 (CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE))
47#define PHYS_SDRAM_8_SIZE SDRAM_BANK_SIZE
48#define PHYS_SDRAM_9 (CONFIG_SYS_SDRAM_BASE + (8 * SDRAM_BANK_SIZE))
49#define PHYS_SDRAM_9_SIZE SDRAM_BANK_SIZE
50#define PHYS_SDRAM_10 (CONFIG_SYS_SDRAM_BASE + (9 * SDRAM_BANK_SIZE))
51#define PHYS_SDRAM_10_SIZE SDRAM_BANK_SIZE
52#define PHYS_SDRAM_11 (CONFIG_SYS_SDRAM_BASE + (10 * SDRAM_BANK_SIZE))
53#define PHYS_SDRAM_11_SIZE SDRAM_BANK_SIZE
54#define PHYS_SDRAM_12 (CONFIG_SYS_SDRAM_BASE + (11 * SDRAM_BANK_SIZE))
55#define PHYS_SDRAM_12_SIZE SDRAM_BANK_SIZE
56
Dzmitry Sankouski0061b6f2021-10-17 13:45:41 +030057#ifndef MEM_LAYOUT_ENV_SETTINGS
58#define MEM_LAYOUT_ENV_SETTINGS \
59 "bootm_size=0x10000000\0" \
60 "bootm_low=0x40000000\0"
61#endif
62
63#ifndef EXYNOS_DEVICE_SETTINGS
64#define EXYNOS_DEVICE_SETTINGS \
65 "stdin=serial\0" \
66 "stdout=serial\0" \
67 "stderr=serial\0"
68#endif
69
70#ifndef EXYNOS_FDTFILE_SETTING
71#define EXYNOS_FDTFILE_SETTING
72#endif
73
Dzmitry Sankouski24e80782022-02-22 21:49:54 +030074/* Cannot use bootdelay > 0, because timer is not working */
Dzmitry Sankouski0061b6f2021-10-17 13:45:41 +030075#define EXTRA_ENV_SETTINGS \
Dzmitry Sankouski24e80782022-02-22 21:49:54 +030076 "bootdelay=0\0" \
77 "bootcmd=source $prevbl_initrd_start_addr:bootscript\0" \
Dzmitry Sankouski0061b6f2021-10-17 13:45:41 +030078 EXYNOS_DEVICE_SETTINGS \
79 EXYNOS_FDTFILE_SETTING \
80 MEM_LAYOUT_ENV_SETTINGS
81
82#define CONFIG_EXTRA_ENV_SETTINGS \
83 EXTRA_ENV_SETTINGS
84
85#endif /* __CONFIG_EXYNOS78x0_COMMON_H */