| Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| Simon Glass | 14e27ab | 2014-10-07 22:01:45 -0600 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (C) 2013 Samsung Electronics |
| 4 | * |
| 5 | * Common configuration settings for the SAMSUNG EXYNOS boards. |
| Simon Glass | 14e27ab | 2014-10-07 22:01:45 -0600 | [diff] [blame] | 6 | */ |
| 7 | |
| 8 | #ifndef __EXYNOS_COMMON_H |
| 9 | #define __EXYNOS_COMMON_H |
| 10 | |
| 11 | /* High Level Configuration Options */ |
| 12 | #define CONFIG_SAMSUNG /* in a SAMSUNG core */ |
| 13 | #define CONFIG_S5P /* S5P Family */ |
| 14 | |
| 15 | #include <asm/arch/cpu.h> /* get chip and board defs */ |
| 16 | #include <linux/sizes.h> |
| Simon Glass | fb64e36 | 2020-05-10 11:40:09 -0600 | [diff] [blame] | 17 | #include <linux/stringify.h> |
| Simon Glass | 14e27ab | 2014-10-07 22:01:45 -0600 | [diff] [blame] | 18 | |
| Simon Glass | 14e27ab | 2014-10-07 22:01:45 -0600 | [diff] [blame] | 19 | /* Keep L2 Cache Disabled */ |
| Simon Glass | 14e27ab | 2014-10-07 22:01:45 -0600 | [diff] [blame] | 20 | |
| 21 | /* input clock of PLL: 24MHz input clock */ |
| Simon Glass | 14e27ab | 2014-10-07 22:01:45 -0600 | [diff] [blame] | 22 | |
| Simon Glass | 14e27ab | 2014-10-07 22:01:45 -0600 | [diff] [blame] | 23 | /* select serial console configuration */ |
| Simon Glass | 14e27ab | 2014-10-07 22:01:45 -0600 | [diff] [blame] | 24 | |
| Simon Glass | 14e27ab | 2014-10-07 22:01:45 -0600 | [diff] [blame] | 25 | /* PWM */ |
| 26 | #define CONFIG_PWM |
| 27 | |
| Simon Glass | 14e27ab | 2014-10-07 22:01:45 -0600 | [diff] [blame] | 28 | /* Miscellaneous configurable options */ |
| Simon Glass | 14e27ab | 2014-10-07 22:01:45 -0600 | [diff] [blame] | 29 | |
| Simon Glass | 14e27ab | 2014-10-07 22:01:45 -0600 | [diff] [blame] | 30 | #endif /* __CONFIG_H */ |