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git01.mediatek.com / filogic / uboot / c69b30942c6800cc0d481b1e686d9e85e201e062 / . / drivers / video / sunxi / tve.c
blob: adea78a69aa9ff538aa6e60174244b879df3615c [file] [log] [blame]
Jernej Skrabec8531d082017-05-10 18:46:28 +0200[diff] [blame]1/*
2 * TV encoder driver for Allwinner SoCs.
3 *
4 * (C) Copyright 2013-2014 Luc Verhaegen <libv@skynet.be>
5 * (C) Copyright 2014-2015 Hans de Goede <hdegoede@redhat.com>
6 * (C) Copyright 2017 Jernej Skrabec <jernej.skrabec@siol.net>
7 *
8 * SPDX-License-Identifier: GPL-2.0+
9 */
10
11#include <common.h>
12
13#include <asm/arch/tve.h>
14#include <asm/io.h>
15
16void tvencoder_mode_set(struct sunxi_tve_reg * const tve, enum tve_mode mode)
17{
18 switch (mode) {
19 case tve_mode_vga:
20 writel(SUNXI_TVE_GCTRL_DAC_INPUT(0, 1) |
21 SUNXI_TVE_GCTRL_DAC_INPUT(1, 2) |
22 SUNXI_TVE_GCTRL_DAC_INPUT(2, 3), &tve->gctrl);
23 writel(SUNXI_TVE_CFG0_VGA, &tve->cfg0);
24 writel(SUNXI_TVE_DAC_CFG0_VGA, &tve->dac_cfg0);
25 writel(SUNXI_TVE_UNKNOWN1_VGA, &tve->unknown1);
26 break;
27 case tve_mode_composite_pal_nc:
28 writel(SUNXI_TVE_CHROMA_FREQ_PAL_NC, &tve->chroma_freq);
29 /* Fall through */
30 case tve_mode_composite_pal:
31 writel(SUNXI_TVE_GCTRL_DAC_INPUT(0, 1) |
32 SUNXI_TVE_GCTRL_DAC_INPUT(1, 2) |
33 SUNXI_TVE_GCTRL_DAC_INPUT(2, 3) |
34 SUNXI_TVE_GCTRL_DAC_INPUT(3, 4), &tve->gctrl);
35 writel(SUNXI_TVE_CFG0_PAL, &tve->cfg0);
36 writel(SUNXI_TVE_DAC_CFG0_COMPOSITE, &tve->dac_cfg0);
37 writel(SUNXI_TVE_FILTER_COMPOSITE, &tve->filter);
38 writel(SUNXI_TVE_PORCH_NUM_PAL, &tve->porch_num);
39 writel(SUNXI_TVE_LINE_NUM_PAL, &tve->line_num);
40 writel(SUNXI_TVE_BLANK_BLACK_LEVEL_PAL,
41 &tve->blank_black_level);
42 writel(SUNXI_TVE_UNKNOWN1_COMPOSITE, &tve->unknown1);
43 writel(SUNXI_TVE_CBR_LEVEL_PAL, &tve->cbr_level);
44 writel(SUNXI_TVE_BURST_WIDTH_COMPOSITE, &tve->burst_width);
45 writel(SUNXI_TVE_UNKNOWN2_PAL, &tve->unknown2);
46 writel(SUNXI_TVE_ACTIVE_NUM_COMPOSITE, &tve->active_num);
47 writel(SUNXI_TVE_CHROMA_BW_GAIN_COMP, &tve->chroma_bw_gain);
48 writel(SUNXI_TVE_NOTCH_WIDTH_COMPOSITE, &tve->notch_width);
49 writel(SUNXI_TVE_RESYNC_NUM_PAL, &tve->resync_num);
50 writel(SUNXI_TVE_SLAVE_PARA_COMPOSITE, &tve->slave_para);
51 break;
52 case tve_mode_composite_pal_m:
53 writel(SUNXI_TVE_CHROMA_FREQ_PAL_M, &tve->chroma_freq);
54 writel(SUNXI_TVE_COLOR_BURST_PAL_M, &tve->color_burst);
55 /* Fall through */
56 case tve_mode_composite_ntsc:
57 writel(SUNXI_TVE_GCTRL_DAC_INPUT(0, 1) |
58 SUNXI_TVE_GCTRL_DAC_INPUT(1, 2) |
59 SUNXI_TVE_GCTRL_DAC_INPUT(2, 3) |
60 SUNXI_TVE_GCTRL_DAC_INPUT(3, 4), &tve->gctrl);
61 writel(SUNXI_TVE_CFG0_NTSC, &tve->cfg0);
62 writel(SUNXI_TVE_DAC_CFG0_COMPOSITE, &tve->dac_cfg0);
63 writel(SUNXI_TVE_FILTER_COMPOSITE, &tve->filter);
64 writel(SUNXI_TVE_PORCH_NUM_NTSC, &tve->porch_num);
65 writel(SUNXI_TVE_LINE_NUM_NTSC, &tve->line_num);
66 writel(SUNXI_TVE_BLANK_BLACK_LEVEL_NTSC,
67 &tve->blank_black_level);
68 writel(SUNXI_TVE_UNKNOWN1_COMPOSITE, &tve->unknown1);
69 writel(SUNXI_TVE_CBR_LEVEL_NTSC, &tve->cbr_level);
70 writel(SUNXI_TVE_BURST_PHASE_NTSC, &tve->burst_phase);
71 writel(SUNXI_TVE_BURST_WIDTH_COMPOSITE, &tve->burst_width);
72 writel(SUNXI_TVE_UNKNOWN2_NTSC, &tve->unknown2);
73 writel(SUNXI_TVE_SYNC_VBI_LEVEL_NTSC, &tve->sync_vbi_level);
74 writel(SUNXI_TVE_ACTIVE_NUM_COMPOSITE, &tve->active_num);
75 writel(SUNXI_TVE_CHROMA_BW_GAIN_COMP, &tve->chroma_bw_gain);
76 writel(SUNXI_TVE_NOTCH_WIDTH_COMPOSITE, &tve->notch_width);
77 writel(SUNXI_TVE_RESYNC_NUM_NTSC, &tve->resync_num);
78 writel(SUNXI_TVE_SLAVE_PARA_COMPOSITE, &tve->slave_para);
79 break;
80 }
81}
82
83void tvencoder_enable(struct sunxi_tve_reg * const tve)
84{
85 setbits_le32(&tve->gctrl, SUNXI_TVE_GCTRL_ENABLE);
86}