blob: e078fab7b41561d567f44459ba5010b31d60f12a [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Wenyou Yang8c772bd2016-07-20 17:55:12 +08002/*
3 * Copyright (C) 2016 Atmel Corporation
4 * Wenyou.Yang <wenyou.yang@atmel.com>
Wenyou Yang8c772bd2016-07-20 17:55:12 +08005 */
6
7#include <common.h>
8#include <clk-uclass.h>
Simon Glass11c89f32017-05-17 17:18:03 -06009#include <dm.h>
Wenyou Yang8c772bd2016-07-20 17:55:12 +080010
11DECLARE_GLOBAL_DATA_PTR;
12
13static ulong at91_master_clk_get_rate(struct clk *clk)
14{
15 return gd->arch.mck_rate_hz;
16}
17
18static struct clk_ops at91_master_clk_ops = {
19 .get_rate = at91_master_clk_get_rate,
20};
21
22static const struct udevice_id at91_master_clk_match[] = {
Wenyou Yange382e2d2017-04-14 14:53:23 +080023 { .compatible = "atmel,at91rm9200-clk-master" },
Wenyou Yang8c772bd2016-07-20 17:55:12 +080024 { .compatible = "atmel,at91sam9x5-clk-master" },
25 {}
26};
27
Walter Lozano2901ac62020-06-25 01:10:04 -030028U_BOOT_DRIVER(atmel_at91rm9200_clk_master) = {
29 .name = "atmel_at91rm9200_clk_master",
Wenyou Yang8c772bd2016-07-20 17:55:12 +080030 .id = UCLASS_CLK,
31 .of_match = at91_master_clk_match,
32 .ops = &at91_master_clk_ops,
33};