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Daniel Hellstrom207e6952008-03-28 10:00:33 +01001/* Initializes CPU and basic hardware such as memory
2 * controllers, IRQ controller and system timer 0.
3 *
Francois Retiefe3051d92015-10-28 14:29:32 +02004 * (C) Copyright 2007, 2015
5 * Daniel Hellstrom, Cobham Gaisler, daniel@gaisler.com
Daniel Hellstrom207e6952008-03-28 10:00:33 +01006 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02007 * SPDX-License-Identifier: GPL-2.0+
Daniel Hellstrom207e6952008-03-28 10:00:33 +01008 */
9
10#include <common.h>
11#include <asm/asi.h>
12#include <asm/leon.h>
Francois Retief7d07d682015-10-28 15:18:22 +020013#include <asm/io.h>
Daniel Hellstrom207e6952008-03-28 10:00:33 +010014
15#include <config.h>
16
17DECLARE_GLOBAL_DATA_PTR;
18
Daniel Hellstrom207e6952008-03-28 10:00:33 +010019/*
20 * Breath some life into the CPU...
21 *
22 * Set up the memory map,
23 * initialize a bunch of registers.
24 *
25 * Run from FLASH/PROM:
Loïc Minier5d0569a2011-02-03 22:04:26 +010026 * - until memory controller is set up, only registers available
Daniel Hellstrom207e6952008-03-28 10:00:33 +010027 * - no global variables available for writing
Loïc Minier5d0569a2011-02-03 22:04:26 +010028 * - constants available
Daniel Hellstrom207e6952008-03-28 10:00:33 +010029 */
30
31void cpu_init_f(void)
32{
33 LEON2_regs *leon2 = (LEON2_regs *) LEON2_PREGS;
34
35 /* initialize the IRQMP */
36 leon2->Interrupt_Force = 0;
37 leon2->Interrupt_Pending = 0;
38 leon2->Interrupt_Clear = 0xfffe; /* clear all old pending interrupts */
39 leon2->Interrupt_Mask = 0xfffe0000; /* mask all IRQs */
40
41 /* cache */
42
Francois Retief21ffc1f2015-11-21 17:07:48 +020043 /* I/O port setup */
Daniel Hellstrom207e6952008-03-28 10:00:33 +010044#ifdef LEON2_IO_PORT_DIR
Francois Retief21ffc1f2015-11-21 17:07:48 +020045 leon2->PIO_Direction = LEON2_IO_PORT_DIR;
Daniel Hellstrom207e6952008-03-28 10:00:33 +010046#endif
47#ifdef LEON2_IO_PORT_DATA
Francois Retief21ffc1f2015-11-21 17:07:48 +020048 leon2->PIO_Data = LEON2_IO_PORT_DATA;
Daniel Hellstrom207e6952008-03-28 10:00:33 +010049#endif
50#ifdef LEON2_IO_PORT_INT
Francois Retief21ffc1f2015-11-21 17:07:48 +020051 leon2->PIO_Interrupt = LEON2_IO_PORT_INT;
Daniel Hellstrom207e6952008-03-28 10:00:33 +010052#else
Francois Retief21ffc1f2015-11-21 17:07:48 +020053 leon2->PIO_Interrupt = 0;
Daniel Hellstrom207e6952008-03-28 10:00:33 +010054#endif
Francois Retief7d07d682015-10-28 15:18:22 +020055
56 /* disable timers */
57 leon2->Timer_Control_1 = leon2->Timer_Control_2 = 0;
Daniel Hellstrom207e6952008-03-28 10:00:33 +010058}
59
Francois Retiefe3051d92015-10-28 14:29:32 +020060int arch_cpu_init(void)
61{
62 gd->cpu_clk = CONFIG_SYS_CLK_FREQ;
63 gd->bus_clk = CONFIG_SYS_CLK_FREQ;
64 gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
Daniel Hellstrom207e6952008-03-28 10:00:33 +010065
Francois Retiefe3051d92015-10-28 14:29:32 +020066 return 0;
Daniel Hellstrom207e6952008-03-28 10:00:33 +010067}
68
69/*
Francois Retief7d07d682015-10-28 15:18:22 +020070 * initialize higher level parts of CPU
Daniel Hellstrom207e6952008-03-28 10:00:33 +010071 */
72int cpu_init_r(void)
73{
Francois Retief7d07d682015-10-28 15:18:22 +020074 return 0;
Daniel Hellstrom207e6952008-03-28 10:00:33 +010075}
76
Francois Retieff7a98172015-11-21 23:15:07 +020077/* initiate and setup timer0 to configured HZ. Base clock is 1MHz.
Daniel Hellstrom207e6952008-03-28 10:00:33 +010078 */
Francois Retief7d07d682015-10-28 15:18:22 +020079int timer_init(void)
80{
81 LEON2_regs *leon2 = (LEON2_regs *)LEON2_PREGS;
82
83 /* initialize prescaler common to all timers to 1MHz */
84 leon2->Scaler_Counter = leon2->Scaler_Reload =
85 (((CONFIG_SYS_CLK_FREQ / 1000) + 500) / 1000) - 1;
86
87 /* SYS_HZ ticks per second */
88 leon2->Timer_Counter_1 = 0;
89 leon2->Timer_Reload_1 = (CONFIG_SYS_TIMER_RATE / CONFIG_SYS_HZ) - 1;
90 leon2->Timer_Control_1 = LEON2_TIMER_CTRL_EN | LEON2_TIMER_CTRL_RS |
91 LEON2_TIMER_CTRL_LD;
92
93 CONFIG_SYS_TIMER_COUNTER = (void *)&leon2->Timer_Counter_1;
94 return 0;
95}