blob: e1f9f12523fbc14de459ea74b8814ea343b7af83 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Albert ARIBAUD \(3ADEV\)ee69a392015-03-31 11:40:51 +02002/*
3 * WORK Microwave work_92105 board configuration file
4 *
5 * (C) Copyright 2014 DENX Software Engineering GmbH
6 * Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr>
Albert ARIBAUD \(3ADEV\)ee69a392015-03-31 11:40:51 +02007 */
8
9#ifndef __CONFIG_WORK_92105_H__
10#define __CONFIG_WORK_92105_H__
11
12/* SoC and board defines */
13#include <linux/sizes.h>
14#include <asm/arch/cpu.h>
15
16/*
Albert ARIBAUD \(3ADEV\)ee69a392015-03-31 11:40:51 +020017 * Memory configurations
18 */
Albert ARIBAUD \(3ADEV\)ee69a392015-03-31 11:40:51 +020019#define CONFIG_SYS_SDRAM_BASE EMC_DYCS0_BASE
20#define CONFIG_SYS_SDRAM_SIZE SZ_128M
Albert ARIBAUD \(3ADEV\)ee69a392015-03-31 11:40:51 +020021
Albert ARIBAUD \(3ADEV\)ee69a392015-03-31 11:40:51 +020022#define CONFIG_RTC_DS1374
23
24/*
Albert ARIBAUD \(3ADEV\)ee69a392015-03-31 11:40:51 +020025 * U-Boot General Configurations
26 */
Albert ARIBAUD \(3ADEV\)ee69a392015-03-31 11:40:51 +020027
Albert ARIBAUD \(3ADEV\)ee69a392015-03-31 11:40:51 +020028/*
Albert ARIBAUD \(3ADEV\)ee69a392015-03-31 11:40:51 +020029 * NAND chip timings for FIXME: which one?
30 */
31
32#define CONFIG_LPC32XX_NAND_MLC_TCEA_DELAY 333333333
33#define CONFIG_LPC32XX_NAND_MLC_BUSY_DELAY 10000000
34#define CONFIG_LPC32XX_NAND_MLC_NAND_TA 18181818
35#define CONFIG_LPC32XX_NAND_MLC_RD_HIGH 31250000
36#define CONFIG_LPC32XX_NAND_MLC_RD_LOW 45454545
37#define CONFIG_LPC32XX_NAND_MLC_WR_HIGH 40000000
38#define CONFIG_LPC32XX_NAND_MLC_WR_LOW 83333333
39
40/*
41 * NAND
42 */
43
44/* driver configuration */
Albert ARIBAUD \(3ADEV\)ee69a392015-03-31 11:40:51 +020045#define CONFIG_SYS_MAX_NAND_CHIPS 1
46#define CONFIG_SYS_NAND_BASE MLC_NAND_BASE
Albert ARIBAUD \(3ADEV\)ee69a392015-03-31 11:40:51 +020047
Albert ARIBAUD \(3ADEV\)ee69a392015-03-31 11:40:51 +020048/*
49 * GPIO
50 */
51
Albert ARIBAUD \(3ADEV\)ee69a392015-03-31 11:40:51 +020052/*
Albert ARIBAUD \(3ADEV\)ee69a392015-03-31 11:40:51 +020053 * Environment
54 */
55
Albert ARIBAUD \(3ADEV\)ee69a392015-03-31 11:40:51 +020056/*
Albert ARIBAUD \(3ADEV\)ee69a392015-03-31 11:40:51 +020057 * SPL
58 */
59
60/* SPL will be executed at offset 0 */
Albert ARIBAUD \(3ADEV\)ee69a392015-03-31 11:40:51 +020061/* SPL will use SRAM as stack */
Albert ARIBAUD \(3ADEV\)ee69a392015-03-31 11:40:51 +020062/* Use the framework and generic lib */
Albert ARIBAUD \(3ADEV\)ee69a392015-03-31 11:40:51 +020063/* SPL will use serial */
Albert ARIBAUD \(3ADEV\)ee69a392015-03-31 11:40:51 +020064/* SPL will load U-Boot from NAND offset 0x40000 */
Simon Glass72cc5382022-10-20 18:22:39 -060065/* U-Boot will be 0x40000 bytes, loaded and run at CONFIG_TEXT_BASE */
Albert ARIBAUD \(3ADEV\)ee69a392015-03-31 11:40:51 +020066#define CONFIG_SYS_MONITOR_LEN 0x40000 /* actually, MAX size */
Simon Glass72cc5382022-10-20 18:22:39 -060067#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE
68#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_TEXT_BASE
Albert ARIBAUD \(3ADEV\)ee69a392015-03-31 11:40:51 +020069
70/*
71 * Include SoC specific configuration
72 */
73#include <asm/arch/config.h>
74
75#endif /* __CONFIG_WORK_92105_H__*/