blob: fd69dc41a86e9e7d063f6cb1390eedd29590ac90 [file] [log] [blame]
Teresa Remmet82750c22020-08-21 09:55:53 +02001/* SPDX-License-Identifier: GPL-2.0-or-later
2 *
3 * Copyright (C) 2019-2020 PHYTEC Messtechnik GmbH
4 * Author: Teresa Remmet <t.remmet@phytec.de>
5 */
6
7#ifndef __PHYCORE_IMX8MM_H
8#define __PHYCORE_IMX8MM_H
9
10#include <linux/sizes.h>
11#include <linux/stringify.h>
12#include <asm/arch/imx-regs.h>
13
14#define CONFIG_SYS_BOOTM_LEN SZ_64M
15#define CONFIG_SPL_MAX_SIZE (148 * SZ_1K)
16#define CONFIG_SYS_MONITOR_LEN SZ_512K
17#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
18#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300
19#define CONFIG_SYS_UBOOT_BASE \
20 (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
21
22#ifdef CONFIG_SPL_BUILD
23#define CONFIG_SPL_STACK 0x920000
24#define CONFIG_SPL_BSS_START_ADDR 0x910000
25#define CONFIG_SPL_BSS_MAX_SIZE SZ_8K
26#define CONFIG_SYS_SPL_MALLOC_START 0x42200000
27#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K
28
29/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
30#define CONFIG_MALLOC_F_ADDR 0x930000
31/* For RAW image gives a error info not panic */
32#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
33#endif
34
35#define CONFIG_EXTRA_ENV_SETTINGS \
36 "image=Image\0" \
37 "console=ttymxc2,115200\0" \
38 "fdt_addr=0x48000000\0" \
39 "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
40 "ipaddr=192.168.3.11\0" \
41 "serverip=192.168.3.10\0" \
42 "netmask=255.225.255.0\0" \
43 "ip_dyn=no\0" \
44 "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
45 "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
46 "mmcroot=2\0" \
47 "mmcautodetect=yes\0" \
48 "mmcargs=setenv bootargs console=${console} " \
49 "root=/dev/mmcblk${mmcdev}p${mmcroot} rootwait rw\0" \
50 "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
51 "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
52 "mmcboot=echo Booting from mmc ...; " \
53 "run mmcargs; " \
54 "if run loadfdt; then " \
55 "booti ${loadaddr} - ${fdt_addr}; " \
56 "else " \
57 "echo WARN: Cannot load the DT; " \
58 "fi;\0 " \
59 "nfsroot=/nfs\0" \
60 "netargs=setenv bootargs console=${console} root=/dev/nfs ip=dhcp " \
61 "nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
62 "netboot=echo Booting from net ...; " \
63 "run netargs; " \
64 "if test ${ip_dyn} = yes; then " \
65 "setenv get_cmd dhcp; " \
66 "else " \
67 "setenv get_cmd tftp; " \
68 "fi; " \
69 "${get_cmd} ${loadaddr} ${image}; " \
70 "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
71 "booti ${loadaddr} - ${fdt_addr}; " \
72 "else " \
73 "echo WARN: Cannot load the DT; " \
74 "fi;\0" \
75
76#define CONFIG_BOOTCOMMAND \
77 "mmc dev ${mmcdev}; if mmc rescan; then " \
78 "if run loadimage; then " \
79 "run mmcboot; " \
80 "else run netboot; " \
81 "fi; " \
82 "fi;"
83
84/* Link Definitions */
85#define CONFIG_LOADADDR 0x40480000
86#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
87
88#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
89#define CONFIG_SYS_INIT_RAM_SIZE SZ_512K
90#define CONFIG_SYS_INIT_SP_OFFSET \
91 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
92#define CONFIG_SYS_INIT_SP_ADDR \
93 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
94
95#define CONFIG_MMCROOT "/dev/mmcblk2p2" /* USDHC3 */
96
97/* Size of malloc() pool */
98#define CONFIG_SYS_MALLOC_LEN SZ_32M
99#define CONFIG_SYS_SDRAM_BASE 0x40000000
100
101#define PHYS_SDRAM SZ_1G
102#define PHYS_SDRAM_SIZE SZ_2G /* 2GB DDR */
103
104/* UART */
105#define CONFIG_MXC_UART_BASE UART3_BASE_ADDR
106
107/* Monitor Command Prompt */
108#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
109#define CONFIG_SYS_CBSIZE SZ_2K
110#define CONFIG_SYS_MAXARGS 64
111#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
112#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
113 sizeof(CONFIG_SYS_PROMPT) + 16)
114/* USDHC */
115#define CONFIG_FSL_USDHC
116#define CONFIG_SYS_FSL_USDHC_NUM 2
117#define CONFIG_SYS_FSL_ESDHC_ADDR 0
118#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
119
120/* I2C */
121#define CONFIG_SYS_I2C_SPEED 100000
122
123/* ENET1 */
124#define CONFIG_ETHPRIME "FEC"
125#define CONFIG_FEC_XCV_TYPE RGMII
126#define CONFIG_FEC_MXC_PHYADDR 0
127#define FEC_QUIRK_ENET_MAC
128#define IMX_FEC_BASE 0x30BE0000
129
130#endif /* __PHYCORE_IMX8MM_H */