wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 1 | /* |
wdenk | a445ddf | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 2 | * Copyright 2004 Freescale Semiconductor. |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 3 | * (C) Copyright 2003,Motorola Inc. |
| 4 | * Xianghua Xiao, (X.Xiao@motorola.com) |
| 5 | * |
| 6 | * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com> |
| 7 | * |
| 8 | * See file CREDITS for list of people who contributed to this |
| 9 | * project. |
| 10 | * |
| 11 | * This program is free software; you can redistribute it and/or |
| 12 | * modify it under the terms of the GNU General Public License as |
| 13 | * published by the Free Software Foundation; either version 2 of |
| 14 | * the License, or (at your option) any later version. |
| 15 | * |
| 16 | * This program is distributed in the hope that it will be useful, |
| 17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 19 | * GNU General Public License for more details. |
| 20 | * |
| 21 | * You should have received a copy of the GNU General Public License |
| 22 | * along with this program; if not, write to the Free Software |
| 23 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 24 | * MA 02111-1307 USA |
| 25 | */ |
| 26 | |
| 27 | |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 28 | #include <common.h> |
wdenk | 492b9e7 | 2004-08-01 23:02:45 +0000 | [diff] [blame] | 29 | #include <pci.h> |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 30 | #include <asm/processor.h> |
Jon Loeliger | 99d5071 | 2008-03-18 11:12:44 -0500 | [diff] [blame] | 31 | #include <asm/mmu.h> |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 32 | #include <asm/immap_85xx.h> |
Jon Loeliger | 99d5071 | 2008-03-18 11:12:44 -0500 | [diff] [blame] | 33 | #include <asm/fsl_ddr_sdram.h> |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 34 | #include <ioports.h> |
Jon Loeliger | de9737d | 2008-03-04 10:03:03 -0600 | [diff] [blame] | 35 | #include <spd_sdram.h> |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 36 | #include <miiphy.h> |
Kumar Gala | f2982fa | 2007-11-28 22:40:31 -0600 | [diff] [blame] | 37 | #include <libfdt.h> |
| 38 | #include <fdt_support.h> |
Kumar Gala | 727c6a6 | 2009-03-26 01:34:38 -0500 | [diff] [blame] | 39 | #include <asm/fsl_lbc.h> |
Jon Loeliger | 249688a | 2006-10-20 15:54:34 -0500 | [diff] [blame] | 40 | |
Jon Loeliger | 77a4f6e | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 41 | #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) |
wdenk | 13eb221 | 2004-07-09 23:27:13 +0000 | [diff] [blame] | 42 | extern void ddr_enable_ecc(unsigned int dram_size); |
| 43 | #endif |
| 44 | |
wdenk | 13eb221 | 2004-07-09 23:27:13 +0000 | [diff] [blame] | 45 | |
wdenk | 492b9e7 | 2004-08-01 23:02:45 +0000 | [diff] [blame] | 46 | void local_bus_init(void); |
wdenk | 13eb221 | 2004-07-09 23:27:13 +0000 | [diff] [blame] | 47 | |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 48 | |
| 49 | /* |
| 50 | * I/O Port configuration table |
| 51 | * |
| 52 | * if conf is 1, then that port pin will be configured at boot time |
| 53 | * according to the five values podr/pdir/ppar/psor/pdat for that entry |
| 54 | */ |
| 55 | |
| 56 | const iop_conf_t iop_conf_tab[4][32] = { |
| 57 | |
| 58 | /* Port A configuration */ |
| 59 | { /* conf ppar psor pdir podr pdat */ |
| 60 | /* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */ |
| 61 | /* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */ |
| 62 | /* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */ |
| 63 | /* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */ |
| 64 | /* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */ |
| 65 | /* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */ |
| 66 | /* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */ |
| 67 | /* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */ |
| 68 | /* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */ |
| 69 | /* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */ |
| 70 | /* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */ |
| 71 | /* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */ |
| 72 | /* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */ |
| 73 | /* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */ |
| 74 | /* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */ |
| 75 | /* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */ |
| 76 | /* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */ |
| 77 | /* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */ |
| 78 | /* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */ |
| 79 | /* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */ |
| 80 | /* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */ |
| 81 | /* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */ |
| 82 | /* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */ |
| 83 | /* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */ |
| 84 | /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */ |
| 85 | /* PA6 */ { 0, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */ |
| 86 | /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */ |
| 87 | /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */ |
| 88 | /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */ |
| 89 | /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */ |
| 90 | /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FREERUN */ |
| 91 | /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */ |
| 92 | }, |
| 93 | |
| 94 | /* Port B configuration */ |
| 95 | { /* conf ppar psor pdir podr pdat */ |
| 96 | /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ |
| 97 | /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ |
| 98 | /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ |
| 99 | /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ |
| 100 | /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ |
| 101 | /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ |
| 102 | /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ |
| 103 | /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ |
| 104 | /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ |
| 105 | /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ |
| 106 | /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ |
| 107 | /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ |
| 108 | /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ |
| 109 | /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ |
| 110 | /* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */ |
| 111 | /* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */ |
| 112 | /* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */ |
| 113 | /* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */ |
| 114 | /* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */ |
| 115 | /* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */ |
| 116 | /* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ |
| 117 | /* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ |
| 118 | /* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ |
| 119 | /* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ |
| 120 | /* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ |
| 121 | /* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ |
| 122 | /* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ |
| 123 | /* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ |
| 124 | /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ |
| 125 | /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ |
| 126 | /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ |
| 127 | /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ |
| 128 | }, |
| 129 | |
| 130 | /* Port C */ |
| 131 | { /* conf ppar psor pdir podr pdat */ |
| 132 | /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */ |
| 133 | /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */ |
| 134 | /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */ |
| 135 | /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */ |
| 136 | /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */ |
| 137 | /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */ |
| 138 | /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */ |
| 139 | /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */ |
| 140 | /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */ |
| 141 | /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */ |
| 142 | /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */ |
| 143 | /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */ |
| 144 | /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */ |
| 145 | /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */ |
| 146 | /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */ |
| 147 | /* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */ |
| 148 | /* PC15 */ { 1, 1, 0, 0, 0, 0 }, /* PC15 */ |
| 149 | /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */ |
| 150 | /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */ |
| 151 | /* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */ |
| 152 | /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */ |
| 153 | /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* FETHMDC */ |
| 154 | /* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* FETHMDIO */ |
| 155 | /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */ |
| 156 | /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */ |
| 157 | /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */ |
| 158 | /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */ |
| 159 | /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */ |
| 160 | /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */ |
| 161 | /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */ |
| 162 | /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */ |
| 163 | /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */ |
| 164 | }, |
| 165 | |
| 166 | /* Port D */ |
| 167 | { /* conf ppar psor pdir podr pdat */ |
| 168 | /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */ |
| 169 | /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */ |
| 170 | /* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */ |
| 171 | /* PD28 */ { 0, 1, 0, 0, 0, 0 }, /* PD28 */ |
| 172 | /* PD27 */ { 0, 1, 1, 1, 0, 0 }, /* PD27 */ |
| 173 | /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */ |
| 174 | /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */ |
| 175 | /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */ |
| 176 | /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */ |
| 177 | /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */ |
| 178 | /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */ |
| 179 | /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */ |
| 180 | /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */ |
| 181 | /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */ |
| 182 | /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */ |
| 183 | /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */ |
| 184 | /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */ |
| 185 | /* PD14 */ { 0, 0, 0, 1, 0, 0 }, /* LED */ |
| 186 | /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */ |
| 187 | /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ |
| 188 | /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ |
| 189 | /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ |
| 190 | /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */ |
| 191 | /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */ |
| 192 | /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */ |
| 193 | /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */ |
| 194 | /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */ |
| 195 | /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */ |
| 196 | /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ |
| 197 | /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ |
| 198 | /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ |
| 199 | /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ |
| 200 | } |
| 201 | }; |
| 202 | |
wdenk | 13eb221 | 2004-07-09 23:27:13 +0000 | [diff] [blame] | 203 | |
| 204 | /* |
| 205 | * MPC8560ADS Board Status & Control Registers |
| 206 | */ |
| 207 | typedef struct bcsr_ { |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 208 | volatile unsigned char bcsr0; |
| 209 | volatile unsigned char bcsr1; |
| 210 | volatile unsigned char bcsr2; |
| 211 | volatile unsigned char bcsr3; |
| 212 | volatile unsigned char bcsr4; |
| 213 | volatile unsigned char bcsr5; |
| 214 | } bcsr_t; |
| 215 | |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 216 | void reset_phy (void) |
| 217 | { |
| 218 | #if defined(CONFIG_ETHER_ON_FCC) /* avoid compile warnings for now */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 219 | volatile bcsr_t *bcsr = (bcsr_t *) CONFIG_SYS_BCSR; |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 220 | #endif |
| 221 | /* reset Giga bit Ethernet port if needed here */ |
| 222 | |
| 223 | /* reset the CPM FEC port */ |
| 224 | #if (CONFIG_ETHER_INDEX == 2) |
| 225 | bcsr->bcsr2 &= ~FETH2_RST; |
| 226 | udelay(2); |
| 227 | bcsr->bcsr2 |= FETH2_RST; |
| 228 | udelay(1000); |
| 229 | #elif (CONFIG_ETHER_INDEX == 3) |
| 230 | bcsr->bcsr3 &= ~FETH3_RST; |
| 231 | udelay(2); |
| 232 | bcsr->bcsr3 |= FETH3_RST; |
| 233 | udelay(1000); |
| 234 | #endif |
| 235 | #if defined(CONFIG_MII) && defined(CONFIG_ETHER_ON_FCC) |
Marian Balakowicz | aab8c49 | 2005-10-28 22:30:33 +0200 | [diff] [blame] | 236 | /* reset PHY */ |
Heiko Schocher | c5e8405 | 2010-07-20 17:45:02 +0200 | [diff] [blame] | 237 | miiphy_reset("FCC1", 0x0); |
Marian Balakowicz | aab8c49 | 2005-10-28 22:30:33 +0200 | [diff] [blame] | 238 | |
| 239 | /* change PHY address to 0x02 */ |
Mike Frysinger | d63ee71 | 2010-12-23 15:40:12 -0500 | [diff] [blame] | 240 | bb_miiphy_write(NULL, 0, MII_MIPSCR, 0xf028); |
Marian Balakowicz | aab8c49 | 2005-10-28 22:30:33 +0200 | [diff] [blame] | 241 | |
Mike Frysinger | d63ee71 | 2010-12-23 15:40:12 -0500 | [diff] [blame] | 242 | bb_miiphy_write(NULL, 0x02, MII_BMCR, |
| 243 | BMCR_ANENABLE | BMCR_ANRESTART); |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 244 | #endif /* CONFIG_MII */ |
| 245 | } |
| 246 | |
wdenk | 492b9e7 | 2004-08-01 23:02:45 +0000 | [diff] [blame] | 247 | |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 248 | int checkboard (void) |
| 249 | { |
wdenk | a445ddf | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 250 | puts("Board: ADS\n"); |
wdenk | 13eb221 | 2004-07-09 23:27:13 +0000 | [diff] [blame] | 251 | |
| 252 | #ifdef CONFIG_PCI |
Peter Tyser | 2b91f71 | 2010-10-29 17:59:24 -0500 | [diff] [blame] | 253 | printf("PCI1: 32 bit, %d MHz (compiled)\n", |
wdenk | 13eb221 | 2004-07-09 23:27:13 +0000 | [diff] [blame] | 254 | CONFIG_SYS_CLK_FREQ / 1000000); |
| 255 | #else |
Peter Tyser | 2b91f71 | 2010-10-29 17:59:24 -0500 | [diff] [blame] | 256 | printf("PCI1: disabled\n"); |
wdenk | 13eb221 | 2004-07-09 23:27:13 +0000 | [diff] [blame] | 257 | #endif |
wdenk | 492b9e7 | 2004-08-01 23:02:45 +0000 | [diff] [blame] | 258 | |
| 259 | /* |
| 260 | * Initialize local bus. |
| 261 | */ |
| 262 | local_bus_init(); |
| 263 | |
wdenk | a445ddf | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 264 | return 0; |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 265 | } |
| 266 | |
wdenk | 13eb221 | 2004-07-09 23:27:13 +0000 | [diff] [blame] | 267 | /* |
wdenk | 492b9e7 | 2004-08-01 23:02:45 +0000 | [diff] [blame] | 268 | * Initialize Local Bus |
wdenk | 13eb221 | 2004-07-09 23:27:13 +0000 | [diff] [blame] | 269 | */ |
| 270 | |
wdenk | 492b9e7 | 2004-08-01 23:02:45 +0000 | [diff] [blame] | 271 | void |
| 272 | local_bus_init(void) |
wdenk | 13eb221 | 2004-07-09 23:27:13 +0000 | [diff] [blame] | 273 | { |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 274 | volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); |
Becky Bruce | 0d4cee1 | 2010-06-17 11:37:20 -0500 | [diff] [blame] | 275 | volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; |
wdenk | 13eb221 | 2004-07-09 23:27:13 +0000 | [diff] [blame] | 276 | |
wdenk | 492b9e7 | 2004-08-01 23:02:45 +0000 | [diff] [blame] | 277 | uint clkdiv; |
| 278 | uint lbc_hz; |
| 279 | sys_info_t sysinfo; |
wdenk | 13eb221 | 2004-07-09 23:27:13 +0000 | [diff] [blame] | 280 | |
| 281 | /* |
wdenk | 492b9e7 | 2004-08-01 23:02:45 +0000 | [diff] [blame] | 282 | * Errata LBC11. |
| 283 | * Fix Local Bus clock glitch when DLL is enabled. |
wdenk | 13eb221 | 2004-07-09 23:27:13 +0000 | [diff] [blame] | 284 | * |
Wolfgang Denk | af0501a | 2008-10-19 02:35:50 +0200 | [diff] [blame] | 285 | * If localbus freq is < 66MHz, DLL bypass mode must be used. |
| 286 | * If localbus freq is > 133MHz, DLL can be safely enabled. |
wdenk | 492b9e7 | 2004-08-01 23:02:45 +0000 | [diff] [blame] | 287 | * Between 66 and 133, the DLL is enabled with an override workaround. |
wdenk | 13eb221 | 2004-07-09 23:27:13 +0000 | [diff] [blame] | 288 | */ |
wdenk | 492b9e7 | 2004-08-01 23:02:45 +0000 | [diff] [blame] | 289 | |
| 290 | get_sys_info(&sysinfo); |
Trent Piepho | 1b560ac | 2008-12-03 15:16:34 -0800 | [diff] [blame] | 291 | clkdiv = lbc->lcrr & LCRR_CLKDIV; |
wdenk | 492b9e7 | 2004-08-01 23:02:45 +0000 | [diff] [blame] | 292 | lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; |
| 293 | |
| 294 | if (lbc_hz < 66) { |
Paul Gortmaker | e5b89d5 | 2012-08-13 13:48:57 +0000 | [diff] [blame] | 295 | lbc->lcrr = CONFIG_SYS_LBC_LCRR | LCRR_DBYP; /* DLL Bypass */ |
wdenk | 492b9e7 | 2004-08-01 23:02:45 +0000 | [diff] [blame] | 296 | |
| 297 | } else if (lbc_hz >= 133) { |
Paul Gortmaker | e5b89d5 | 2012-08-13 13:48:57 +0000 | [diff] [blame] | 298 | lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~LCRR_DBYP); /* DLL Enabled */ |
wdenk | 13eb221 | 2004-07-09 23:27:13 +0000 | [diff] [blame] | 299 | |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 300 | } else { |
wdenk | 13eb221 | 2004-07-09 23:27:13 +0000 | [diff] [blame] | 301 | /* |
| 302 | * On REV1 boards, need to change CLKDIV before enable DLL. |
| 303 | * Default CLKDIV is 8, change it to 4 temporarily. |
| 304 | */ |
wdenk | 492b9e7 | 2004-08-01 23:02:45 +0000 | [diff] [blame] | 305 | uint pvr = get_pvr(); |
wdenk | 13eb221 | 2004-07-09 23:27:13 +0000 | [diff] [blame] | 306 | uint temp_lbcdll = 0; |
wdenk | a445ddf | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 307 | |
| 308 | if (pvr == PVR_85xx_REV1) { |
wdenk | 492b9e7 | 2004-08-01 23:02:45 +0000 | [diff] [blame] | 309 | /* FIXME: Justify the high bit here. */ |
wdenk | 13eb221 | 2004-07-09 23:27:13 +0000 | [diff] [blame] | 310 | lbc->lcrr = 0x10000004; |
wdenk | a445ddf | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 311 | } |
wdenk | 13eb221 | 2004-07-09 23:27:13 +0000 | [diff] [blame] | 312 | |
Paul Gortmaker | e5b89d5 | 2012-08-13 13:48:57 +0000 | [diff] [blame] | 313 | lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~LCRR_DBYP);/* DLL Enabled */ |
wdenk | 492b9e7 | 2004-08-01 23:02:45 +0000 | [diff] [blame] | 314 | udelay(200); |
| 315 | |
| 316 | /* |
| 317 | * Sample LBC DLL ctrl reg, upshift it to set the |
| 318 | * override bits. |
| 319 | */ |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 320 | temp_lbcdll = gur->lbcdllcr; |
wdenk | 492b9e7 | 2004-08-01 23:02:45 +0000 | [diff] [blame] | 321 | gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000); |
| 322 | asm("sync;isync;msync"); |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 323 | } |
wdenk | 492b9e7 | 2004-08-01 23:02:45 +0000 | [diff] [blame] | 324 | } |
| 325 | |
| 326 | |
| 327 | /* |
| 328 | * Initialize SDRAM memory on the Local Bus. |
| 329 | */ |
Becky Bruce | b88d3d0 | 2010-12-17 17:17:57 -0600 | [diff] [blame] | 330 | void lbc_sdram_init(void) |
wdenk | 492b9e7 | 2004-08-01 23:02:45 +0000 | [diff] [blame] | 331 | { |
Becky Bruce | 0d4cee1 | 2010-06-17 11:37:20 -0500 | [diff] [blame] | 332 | volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 333 | uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE; |
wdenk | 492b9e7 | 2004-08-01 23:02:45 +0000 | [diff] [blame] | 334 | |
Becky Bruce | 2d8ecac | 2010-12-17 17:17:59 -0600 | [diff] [blame] | 335 | puts("LBC SDRAM: "); |
| 336 | print_size(CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, |
| 337 | "\n "); |
wdenk | 13eb221 | 2004-07-09 23:27:13 +0000 | [diff] [blame] | 338 | |
| 339 | /* |
| 340 | * Setup SDRAM Base and Option Registers |
| 341 | */ |
Becky Bruce | 0d4cee1 | 2010-06-17 11:37:20 -0500 | [diff] [blame] | 342 | set_lbc_or(2, CONFIG_SYS_OR2_PRELIM); |
| 343 | set_lbc_br(2, CONFIG_SYS_BR2_PRELIM); |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 344 | lbc->lbcr = CONFIG_SYS_LBC_LBCR; |
wdenk | 492b9e7 | 2004-08-01 23:02:45 +0000 | [diff] [blame] | 345 | asm("msync"); |
wdenk | 13eb221 | 2004-07-09 23:27:13 +0000 | [diff] [blame] | 346 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 347 | lbc->lsrt = CONFIG_SYS_LBC_LSRT; |
| 348 | lbc->mrtpr = CONFIG_SYS_LBC_MRTPR; |
wdenk | 492b9e7 | 2004-08-01 23:02:45 +0000 | [diff] [blame] | 349 | asm("sync"); |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 350 | |
wdenk | 13eb221 | 2004-07-09 23:27:13 +0000 | [diff] [blame] | 351 | /* |
| 352 | * Configure the SDRAM controller. |
| 353 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 354 | lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1; |
wdenk | 492b9e7 | 2004-08-01 23:02:45 +0000 | [diff] [blame] | 355 | asm("sync"); |
wdenk | 13eb221 | 2004-07-09 23:27:13 +0000 | [diff] [blame] | 356 | *sdram_addr = 0xff; |
wdenk | 492b9e7 | 2004-08-01 23:02:45 +0000 | [diff] [blame] | 357 | ppcDcbf((unsigned long) sdram_addr); |
| 358 | udelay(100); |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 359 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 360 | lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2; |
wdenk | 492b9e7 | 2004-08-01 23:02:45 +0000 | [diff] [blame] | 361 | asm("sync"); |
wdenk | 13eb221 | 2004-07-09 23:27:13 +0000 | [diff] [blame] | 362 | *sdram_addr = 0xff; |
wdenk | 492b9e7 | 2004-08-01 23:02:45 +0000 | [diff] [blame] | 363 | ppcDcbf((unsigned long) sdram_addr); |
| 364 | udelay(100); |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 365 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 366 | lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_3; |
wdenk | 492b9e7 | 2004-08-01 23:02:45 +0000 | [diff] [blame] | 367 | asm("sync"); |
wdenk | 13eb221 | 2004-07-09 23:27:13 +0000 | [diff] [blame] | 368 | *sdram_addr = 0xff; |
wdenk | 492b9e7 | 2004-08-01 23:02:45 +0000 | [diff] [blame] | 369 | ppcDcbf((unsigned long) sdram_addr); |
| 370 | udelay(100); |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 371 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 372 | lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4; |
wdenk | 492b9e7 | 2004-08-01 23:02:45 +0000 | [diff] [blame] | 373 | asm("sync"); |
wdenk | 13eb221 | 2004-07-09 23:27:13 +0000 | [diff] [blame] | 374 | *sdram_addr = 0xff; |
wdenk | 492b9e7 | 2004-08-01 23:02:45 +0000 | [diff] [blame] | 375 | ppcDcbf((unsigned long) sdram_addr); |
| 376 | udelay(100); |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 377 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 378 | lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; |
wdenk | 492b9e7 | 2004-08-01 23:02:45 +0000 | [diff] [blame] | 379 | asm("sync"); |
wdenk | 13eb221 | 2004-07-09 23:27:13 +0000 | [diff] [blame] | 380 | *sdram_addr = 0xff; |
wdenk | 492b9e7 | 2004-08-01 23:02:45 +0000 | [diff] [blame] | 381 | ppcDcbf((unsigned long) sdram_addr); |
| 382 | udelay(100); |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 383 | } |
| 384 | |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 385 | #if !defined(CONFIG_SPD_EEPROM) |
| 386 | /************************************************************************* |
| 387 | * fixed sdram init -- doesn't use serial presence detect. |
| 388 | ************************************************************************/ |
Becky Bruce | 5e35d8a | 2010-12-17 17:17:56 -0600 | [diff] [blame] | 389 | phys_size_t fixed_sdram(void) |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 390 | { |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 391 | #ifndef CONFIG_SYS_RAMBOOT |
Andy Fleming | 992562c | 2012-10-23 19:03:46 -0500 | [diff] [blame] | 392 | volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC8xxx_DDR_ADDR); |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 393 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 394 | ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS; |
| 395 | ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG; |
| 396 | ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; |
| 397 | ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; |
| 398 | ddr->sdram_mode = CONFIG_SYS_DDR_MODE; |
| 399 | ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL; |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 400 | #if defined (CONFIG_DDR_ECC) |
| 401 | ddr->err_disable = 0x0000000D; |
| 402 | ddr->err_sbe = 0x00ff0000; |
| 403 | #endif |
| 404 | asm("sync;isync;msync"); |
| 405 | udelay(500); |
| 406 | #if defined (CONFIG_DDR_ECC) |
| 407 | /* Enable ECC checking */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 408 | ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000); |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 409 | #else |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 410 | ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL; |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 411 | #endif |
| 412 | asm("sync; isync; msync"); |
| 413 | udelay(500); |
| 414 | #endif |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 415 | return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 416 | } |
| 417 | #endif /* !defined(CONFIG_SPD_EEPROM) */ |
wdenk | 492b9e7 | 2004-08-01 23:02:45 +0000 | [diff] [blame] | 418 | |
| 419 | |
| 420 | #if defined(CONFIG_PCI) |
| 421 | /* |
| 422 | * Initialize PCI Devices, report devices found. |
| 423 | */ |
| 424 | |
| 425 | #ifndef CONFIG_PCI_PNP |
| 426 | static struct pci_config_table pci_mpc85xxads_config_table[] = { |
| 427 | { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, |
| 428 | PCI_IDSEL_NUMBER, PCI_ANY_ID, |
| 429 | pci_cfgfunc_config_device, { PCI_ENET0_IOADDR, |
| 430 | PCI_ENET0_MEMADDR, |
| 431 | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
| 432 | } }, |
| 433 | { } |
| 434 | }; |
| 435 | #endif |
| 436 | |
| 437 | |
| 438 | static struct pci_controller hose = { |
| 439 | #ifndef CONFIG_PCI_PNP |
| 440 | config_table: pci_mpc85xxads_config_table, |
| 441 | #endif |
| 442 | }; |
| 443 | |
| 444 | #endif /* CONFIG_PCI */ |
| 445 | |
| 446 | |
| 447 | void |
| 448 | pci_init_board(void) |
| 449 | { |
| 450 | #ifdef CONFIG_PCI |
wdenk | 492b9e7 | 2004-08-01 23:02:45 +0000 | [diff] [blame] | 451 | pci_mpc85xx_init(&hose); |
| 452 | #endif /* CONFIG_PCI */ |
| 453 | } |
Matthew McClintock | 3d40317 | 2006-06-28 10:43:36 -0500 | [diff] [blame] | 454 | |
Andy Fleming | 8ed1196 | 2007-05-08 17:27:43 -0500 | [diff] [blame] | 455 | |
Kumar Gala | f2982fa | 2007-11-28 22:40:31 -0600 | [diff] [blame] | 456 | #if defined(CONFIG_OF_BOARD_SETUP) |
Andy Fleming | 8ed1196 | 2007-05-08 17:27:43 -0500 | [diff] [blame] | 457 | void |
Matthew McClintock | 3d40317 | 2006-06-28 10:43:36 -0500 | [diff] [blame] | 458 | ft_board_setup(void *blob, bd_t *bd) |
| 459 | { |
Kumar Gala | f2982fa | 2007-11-28 22:40:31 -0600 | [diff] [blame] | 460 | int node, tmp[2]; |
| 461 | const char *path; |
| 462 | |
Matthew McClintock | 3d40317 | 2006-06-28 10:43:36 -0500 | [diff] [blame] | 463 | ft_cpu_setup(blob, bd); |
Kumar Gala | f2982fa | 2007-11-28 22:40:31 -0600 | [diff] [blame] | 464 | |
| 465 | node = fdt_path_offset(blob, "/aliases"); |
| 466 | tmp[0] = 0; |
| 467 | if (node >= 0) { |
| 468 | #ifdef CONFIG_PCI |
| 469 | path = fdt_getprop(blob, node, "pci0", NULL); |
| 470 | if (path) { |
| 471 | tmp[1] = hose.last_busno - hose.first_busno; |
| 472 | do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); |
| 473 | } |
| 474 | #endif |
| 475 | } |
Matthew McClintock | 3d40317 | 2006-06-28 10:43:36 -0500 | [diff] [blame] | 476 | } |
| 477 | #endif |