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git01.mediatek.com / filogic / uboot / c609719b8d1b2dca590e0ed499016d041203e403 / . / include / galileo / core.h
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wdenk416fef12002-05-15 20:05:05 +0000[diff] [blame]1/* Core.h - Basic core logic functions and definitions */
2
3/* Copyright Galileo Technology. */
4
5/*
6DESCRIPTION
7This header file contains simple read/write macros for addressing
8the SDRAM, devices, GT`s internal registers and PCI (using the PCI`s address
9space). The macros take care of Big/Little endian conversions.
10*/
11
12#ifndef __INCcoreh
13#define __INCcoreh
14
15/* includes */
16#include "gt64260R.h"
17
18extern unsigned int INTERNAL_REG_BASE_ADDR;
19
20/*
21 * GT-6426x variants
22 */
23#define GT_64260 0 /* includes both 64260A and 64260B */
24#define GT_64261 1
25
26#if (CFG_GT_6426x == GT_64260)
27#ifdef CONFIG_ETHER_PORT_MII
28#define GAL_ETH_DEVS 2
29#else
30#define GAL_ETH_DEVS 3
31#endif
32#elif (CFG_GT_6426x == GT_64261)
33#define GAL_ETH_DEVS 2
34#else
35#define GAL_ETH_DEVS 3 /* default to a 64260 */
36#endif
37
38/****************************************/
39/* GENERAL Definitions */
40/****************************************/
41
42#define NO_BIT 0x00000000
43#define BIT0 0x00000001
44#define BIT1 0x00000002
45#define BIT2 0x00000004
46#define BIT3 0x00000008
47#define BIT4 0x00000010
48#define BIT5 0x00000020
49#define BIT6 0x00000040
50#define BIT7 0x00000080
51#define BIT8 0x00000100
52#define BIT9 0x00000200
53#define BIT10 0x00000400
54#define BIT11 0x00000800
55#define BIT12 0x00001000
56#define BIT13 0x00002000
57#define BIT14 0x00004000
58#define BIT15 0x00008000
59#define BIT16 0x00010000
60#define BIT17 0x00020000
61#define BIT18 0x00040000
62#define BIT19 0x00080000
63#define BIT20 0x00100000
64#define BIT21 0x00200000
65#define BIT22 0x00400000
66#define BIT23 0x00800000
67#define BIT24 0x01000000
68#define BIT25 0x02000000
69#define BIT26 0x04000000
70#define BIT27 0x08000000
71#define BIT28 0x10000000
72#define BIT29 0x20000000
73#define BIT30 0x40000000
74#define BIT31 0x80000000
75
76#define _1K 0x00000400
77#define _2K 0x00000800
78#define _4K 0x00001000
79#define _8K 0x00002000
80#define _16K 0x00004000
81#define _32K 0x00008000
82#define _64K 0x00010000
83#define _128K 0x00020000
84#define _256K 0x00040000
85#define _512K 0x00080000
86
87#define _1M 0x00100000
88#define _2M 0x00200000
89#define _3M 0x00300000
90#define _4M 0x00400000
91#define _5M 0x00500000
92#define _6M 0x00600000
93#define _7M 0x00700000
94#define _8M 0x00800000
95#define _9M 0x00900000
96#define _10M 0x00a00000
97#define _11M 0x00b00000
98#define _12M 0x00c00000
99#define _13M 0x00d00000
100#define _14M 0x00e00000
101#define _15M 0x00f00000
102#define _16M 0x01000000
103
104#define _32M 0x02000000
105#define _64M 0x04000000
106#define _128M 0x08000000
107#define _256M 0x10000000
108#define _512M 0x20000000
109
110#define _1G 0x40000000
111#define _2G 0x80000000
112
113typedef enum _bool{false,true} bool;
114
115/* Little to Big endian conversion macros */
116
117#ifdef LE /* Little Endian */
118#define SHORT_SWAP(X) (X)
119#define WORD_SWAP(X) (X)
120#define LONG_SWAP(X) ((l64)(X))
121
122#else /* Big Endian */
123#define SHORT_SWAP(X) ((X <<8 ) | (X >> 8))
124
125#define WORD_SWAP(X) (((X)&0xff)<<24)+ \
126 (((X)&0xff00)<<8)+ \
127 (((X)&0xff0000)>>8)+ \
128 (((X)&0xff000000)>>24)
129
130#define LONG_SWAP(X) ( (l64) (((X)&0xffULL)<<56)+ \
131 (((X)&0xff00ULL)<<40)+ \
132 (((X)&0xff0000ULL)<<24)+ \
133 (((X)&0xff000000ULL)<<8)+ \
134 (((X)&0xff00000000ULL)>>8)+ \
135 (((X)&0xff0000000000ULL)>>24)+ \
136 (((X)&0xff000000000000ULL)>>40)+ \
137 (((X)&0xff00000000000000ULL)>>56))
138
139#endif
140
141#ifndef NULL
142#define NULL 0
143#endif
144
145/* Those two definitions were defined to be compatible with MIPS */
146#define NONE_CACHEABLE 0x00000000
147#define CACHEABLE 0x00000000
148
149/* 750 cache line */
150#define CACHE_LINE_SIZE 32
151#define CACHELINE_MASK_BITS (CACHE_LINE_SIZE - 1)
152#define CACHELINE_ROUNDUP(A) (((A)+CACHELINE_MASK_BITS) & ~CACHELINE_MASK_BITS)
153
154/* Read/Write to/from GT`s internal registers */
155#define GT_REG_READ(offset, pData) \
156*pData = ( *((volatile unsigned int *)(NONE_CACHEABLE | \
157 INTERNAL_REG_BASE_ADDR | (offset))) ) ; \
158*pData = WORD_SWAP(*pData)
159
160#define GTREGREAD(offset) \
161 (WORD_SWAP( *((volatile unsigned int *)(NONE_CACHEABLE | \
162 INTERNAL_REG_BASE_ADDR | (offset))) ))
163
164#define GT_REG_WRITE(offset, data) \
165*((unsigned int *)( INTERNAL_REG_BASE_ADDR | (offset))) = \
166 WORD_SWAP(data)
167
168/* Write 32/16/8 bit */
169#define WRITE_CHAR(address, data) \
170 *((unsigned char *)(address)) = data
171#define WRITE_SHORT(address, data) \
172 *((unsigned short *)(address)) = data
173#define WRITE_WORD(address, data) \
174 *((unsigned int *)(address)) = data
175
176/* Read 32/16/8 bits - returns data in variable. */
177#define READ_CHAR(address, pData) \
178 *pData = *((volatile unsigned char *)(address))
179
180#define READ_SHORT(address, pData) \
181 *pData = *((volatile unsigned short *)(address))
182
183#define READ_WORD(address, pData) \
184 *pData = *((volatile unsigned int *)(address))
185
186/* Read 32/16/8 bit - returns data direct. */
187#define READCHAR(address) \
188 *((volatile unsigned char *)((address) | NONE_CACHEABLE))
189
190#define READSHORT(address) \
191 *((volatile unsigned short *)((address) | NONE_CACHEABLE))
192
193#define READWORD(address) \
194 *((volatile unsigned int *)((address) | NONE_CACHEABLE))
195
196/* Those two Macros were defined to be compatible with MIPS */
197#define VIRTUAL_TO_PHY(x) (((unsigned int)x) & 0xffffffff)
198#define PHY_TO_VIRTUAL(x) (((unsigned int)x) | NONE_CACHEABLE)
199
200/* SET_REG_BITS(regOffset,bits) -
201 gets register offset and bits: a 32bit value. It set to logic '1' in the
202 internal register the bits which given as an input example:
203 SET_REG_BITS(0x840,BIT3 | BIT24 | BIT30) - set bits: 3,24 and 30 to logic
204 '1' in register 0x840 while the other bits stays as is. */
205#define SET_REG_BITS(regOffset,bits) \
206 *(unsigned int*)(NONE_CACHEABLE | INTERNAL_REG_BASE_ADDR | \
207 regOffset) |= (unsigned int)WORD_SWAP(bits)
208
209/* RESET_REG_BITS(regOffset,bits) -
210 gets register offset and bits: a 32bit value. It set to logic '0' in the
211 internal register the bits which given as an input example:
212 RESET_REG_BITS(0x840,BIT3 | BIT24 | BIT30) - set bits: 3,24 and 30 to logic
213 '0' in register 0x840 while the other bits stays as is. */
214#define RESET_REG_BITS(regOffset,bits) \
215 *(unsigned int*)(NONE_CACHEABLE | INTERNAL_REG_BASE_ADDR \
216 | regOffset) &= ~( (unsigned int)WORD_SWAP(bits) )
217
218#endif /* __INCcoreh */